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The problem of calculating parasitic capacitances is investigated with the main focus put on how to derive the approximate expressions of the capacitances caused at intersections and parallel runs of interconnects. To derive a sim...
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The problem of calculating parasitic capacitances is investigated with the main focus put on how to derive the approximate expressions of the capacitances caused at intersections and parallel runs of interconnects. To derive a simple and accurate approximate expression, the interconnects are divided into a few basic coupling regions, in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance attained by summing the capacitances of these regions proves to be approximated within a relative error of 5% as compared with that obtained by using a 3-D field solver.
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In the design and reliability analysis of SiC capacitive pressure sensors (CPSs), the complex and harsh working environment causes irregular deformation of the sensors, which makes it difficult to analyze the capacitance. In addit...
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In the design and reliability analysis of SiC capacitive pressure sensors (CPSs), the complex and harsh working environment causes irregular deformation of the sensors, which makes it difficult to analyze the capacitance. In addition, when finite element analysis (FEA) software is used for research, multi-physics coupling can be complicated, and different software adopts distinct capacitance analysis processes or even lacks related modules. Through applying the idea of the infinitesimal approach, this paper proposes a model of capacitance calculation for CPSs based on FEA postprocessing, including two mesh processing methods of reflection and densification. First, a SiC sensor is modeled and simulated under environmental stress by using Ansys Workbench. Afterward, the deformation results of the faces and edges of the insulating layers in the capacitor are exported. Then, MATLAB is used for processing the deformation data. Lastly, the capacitance value of the sensor is calculated in accordance with the concept of parallel plate capacitor. The research shows that within the pressure range of 0.5-100 kPa, the error of capacitance values between the proposed model and the theoretical calculation is less than 20%, which reduces to about 7% after the theoretical deviation is corrected; the error between the proposed model and the experiment of the fabricated SiC sensor is 4.7%, and that of capacitance ratio is 3.5%. This calculation model is validated to be suitable for all finite element software for analyzing the performance of different kinds of CPSs.
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A full capacitance model for Amorphous Oxide Semiconductor Thin Film Transistors (AOSTFTs), considering the effect of the drain contact overlap in bottom gate passivated structures is presented. It is shown that this drain overlap...
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A full capacitance model for Amorphous Oxide Semiconductor Thin Film Transistors (AOSTFTs), considering the effect of the drain contact overlap in bottom gate passivated structures is presented. It is shown that this drain overlap, on top of the passivation layer, serves as a second gate with an applied voltage equal to V-DS. When V-DS > V-T the semiconductor-passivation (S-P) interface will be in accumulation and the behavior of the different capacitance is affected. An expression to represent this effect is included in the present model. The overlap capacitance between gate and drain/source, as well as the effect of reducing the channel capacitance as the drain is increased, are also considered by the model. The calculated capacitance is a function of the threshold voltage, (V-T), the mobility and saturation parameters (gamma(a), alpha(s)), and the sharpness of the knee region m, which are extracted using the Unified Model and Extraction Method (UMEM) for AOSTFTs. Results are compared with simulated and experimental data.
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A new method for the determination of parameters for an equivalent electrical circuit model of supercapacitors is proposed. The method is based on the evaluation of the time dependence of voltage measured on the supercapacitor ter...
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A new method for the determination of parameters for an equivalent electrical circuit model of supercapacitors is proposed. The method is based on the evaluation of the time dependence of voltage measured on the supercapacitor terminals after its charging by a defined current pulse. The measured time dependence of the voltage is fitted by an exponential function, where the exponent is proportional to the square root of time. This term reflects the redistribution of charges by diffusion inside the supercapacitor structure. The equivalent electrical circuit of supercapacitors is described by five parameters - two capacitors and three resistors. One capacitor corresponds to the Helmholtz capacitance, which is charged immediately with the time constant in the order of hundreds milliseconds, while the second one represents the diffuse capacitance, which is charged with the time constant in the order of hundreds seconds. The two resistors in the equivalent circuit model represent the equivalent series resistance and the leakage resistance, respectively, while the third resistor describes the resistance for charge diffusion in the supercapacitor structure. This resistance is time dependent and a way for calculating its value is demonstrated. (C) 2015 Elsevier B.V. All rights reserved.
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Analytical expressions for the gate-voltage dependence of the channel capacitance and the gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs) are derived and implemented in an organic compact...
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Analytical expressions for the gate-voltage dependence of the channel capacitance and the gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs) are derived and implemented in an organic compact capacitance model. The resulting modified model is verified by experimental data of transistors with constant mobility. The same model is analyzed by numerical simulations for OTFTs with a voltage-dependent mobility. The simulation results indicate that the quasistatic model describes well the simulated capacitances. In accumulation, the modeled values are slightly overestimated because of the generally accepted assumption of the charge-sheet model. It is also demonstrated that the quasistatic regime occurs at lower frequencies because of the reduced mobility at lower charge carrier concentrations.
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Magnetic induction tomography (MIT) has recently been accomplished using a single inductive sensor, but under the assumption that it behaves as an ideal inductor. When performing a scan with a sensing coil that typically consists ...
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Magnetic induction tomography (MIT) has recently been accomplished using a single inductive sensor, but under the assumption that it behaves as an ideal inductor. When performing a scan with a sensing coil that typically consists of a collection of concentric circular printed circuit board (PCB) copper traces connected in series, small amounts of parasitic capacitance arise that contribute to measured tank circuit loss. Results of this work quantify the magnitude of parasitic capacitance and associated losses. For current inductive sensors, capacitance-related loss is shown to diminish considerably when the coil is positioned more than ~2 cm from a target boundary. Recognizing that single-coil MIT scans generally position the coil within 2 cm of a target boundary, a correction is proposed, which enables a more accurate measurement of true inductive loss. Previously published scan data over agarose phantoms are then reexamined to show the negative impact on imaging fidelity that results when capacitance-related losses are ignored. Image comparisons are made using full 3-D image reconstruction, demonstrating that failure to compensate for parasitic capacitance loss can degrade image fidelity.
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The semiconducting character of graphene and some carbon-based electrodes can lead to noticeably lower total capacitances and stored energy densities in electric double layer (EDL) capacitors. This paper discusses the chemical and...
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The semiconducting character of graphene and some carbon-based electrodes can lead to noticeably lower total capacitances and stored energy densities in electric double layer (EDL) capacitors. This paper discusses the chemical and electronic structure modifications that enhance the available energy bands, density of states and quantum capacitance of graphene substrates near the Fermi level, therefore restoring the conducting character of these materials. The doping of graphene with p or n dopants, such as boron and nitrogen atoms, or the introduction of vacancy defects that introduce zigzag edges, can significantly increase the quantum capacitance within the potential range of interest for the energy storage applications by either shifting the Dirac point away from the Fermi level or by eliminating the Dirac point. We show that a combination of doping and vacancies at realistic concentrations is sufficient to increase the capacitance of a graphene-based electrode to within 1 mu F cm(-2) from that of a metallic surface. Using a combination of ab initio calculations and classical molecular dynamics simulations we estimate how the changes in the quantum capacitance of these electrode materials affect the total capacitance stored by the open structure EDL capacitors containing room temperature ionic liquid electrolytes.
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Current versus voltage measurements were done on copper indium disulphide cells fabricated on a continuous copper tape fabricated at IST (Frankfurt/Oder, D). Temperatures were in the range of 90-370 K. We compared the measurements...
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Current versus voltage measurements were done on copper indium disulphide cells fabricated on a continuous copper tape fabricated at IST (Frankfurt/Oder, D). Temperatures were in the range of 90-370 K. We compared the measurements with an ideal diode model and extracted parameters accordingly. The temperature dependence of the diode ideality factor can give valuable information about the main recombination mechanism in the cell. We find a remarkable agreement of the temperature dependence with a theory derived by Padovani et al. We conclude that tunneling currents play an important role inside the cell.
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Copper indium disulfide cells fabricated on a continuous copper tape fabricated at IST (D) are continuously improving, now reaching efficiencies above 9%, with V_(oc) exceeding 650 mV, and fill factors well above 65%. The internal...
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Copper indium disulfide cells fabricated on a continuous copper tape fabricated at IST (D) are continuously improving, now reaching efficiencies above 9%, with V_(oc) exceeding 650 mV, and fill factors well above 65%. The internal structure of these cells, however, is complicated, and far away from that of an ideal flat and homogeneous crystalline cell: in the depth, there is a sequence of several different layers, which is inherent to this technology; also, lateral inhomogeneities cannot always be precluded. An admittance study was undertaken to characterize the internal electronic cell structure. We carried out C(V,f,T) measurements, i.e. capacitance and conductance vs. voltage and vs. frequency, at temperatures varying between 80 and 300 K. Maxima are observed in the C-V curves at high forward bias voltage. C―f and G―f measurements are interpreted in terms of deep states. The internal consistency of the interpretation of various measurements is validated with numerical simulation (SCAPS programme).
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