摘要 : A sorter-based processor architecture is introduced for digital signal processing purposes. The processor has been optimized to implement sliding average-type linear structures and three- and five-sample sorting operations. The sp... 展开 A sorter-based processor architecture is introduced for digital signal processing purposes. The processor has been optimized to implement sliding average-type linear structures and three- and five-sample sorting operations. The specialized processor can be used, for example, for the several variations of the finite-impulse-response (FIR) median hybrid (FMH) filters, as well as other types of ranked-order filters and running-sum averaging operations. FMH filters with averaging substructures and window lengths of up to 65 samples can be computed with sampling intervals of less than 20 clock cycles. The 12-bit microprogrammable core processor is designed as a full-custom very large scale integration (VLSI) circuit. Examples of filter implementations show that the sorter-based processor architecture is suitable for several kinds of digital signal processing tasks. 收起