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We consider the complexity class ACC (1) and related families of arithmetic circuits. We prove a variety of collapse results, showing several settings in which no loss of computational power results if fan-in of gates is severely ...
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We consider the complexity class ACC (1) and related families of arithmetic circuits. We prove a variety of collapse results, showing several settings in which no loss of computational power results if fan-in of gates is severely restricted, as well as presenting a natural class of arithmetic circuits in which no expressive power is lost by severely restricting the algebraic degree of the circuits. We draw attention to the strong connections that exist between ACC (1) and VP, via connections to the classes CC (1)[m] for various m. These results tend to support a conjecture regarding the computational power of the complexity class VP over finite algebras, and they also highlight the significance of a class of arithmetic circuits that is in some sense dual to VP. In particular, these dual-VP classes provide new characterizations of ACC (1) and TC (1) in terms of circuits of semiunbounded fan-in. As a corollary, we show that ACC (i) = CC (i) for all i >= 1.
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Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several represent...
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Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits.
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We report optimal and asymptotically optimal reversible circuits composed of NOT, CNOT, and Toffoli (NCT) gates, keeping the count by the subsets of the gate types used. This study fine tunes the circuit complexity figures for the...
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We report optimal and asymptotically optimal reversible circuits composed of NOT, CNOT, and Toffoli (NCT) gates, keeping the count by the subsets of the gate types used. This study fine tunes the circuit complexity figures for the realization of reversible functions via reversible NCT circuits. An important consequence is a result on the limitation of the use of the T-count quantum circuit metric popular in applications.
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THE CIRCUIT BREAKERS designed in 1913 for sectionalizing the 11/22-kv 3-wire trolley and feeder circuits on the New Haven Railroad electrification had become inadequate by 1936 because of limited interrupting capacity to clear lin...
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THE CIRCUIT BREAKERS designed in 1913 for sectionalizing the 11/22-kv 3-wire trolley and feeder circuits on the New Haven Railroad electrification had become inadequate by 1936 because of limited interrupting capacity to clear line faults fast enough to insure system stability and reliability. Although these never were designed to handle the entire fault interruption duty, space and weight limitations in the switching stations and supporting structures ruled out their replacement with modern circuit breakers of conventional design for faster fault clearing by line circuit breakers directly. The oil circuit breakers are known as “bridge-type” circuit breakers because of their location on the anchor bridges spanning the railroad tracks and catenary contact system. Figure 1, of a typical switching station, clearly indicates the space and weight limitations involved because of the location of the circuit breakers on the anchor bridges.
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A simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides hig...
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A simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides high isolation from cross-talk at low operating frequencies, its benefit is lost at high frequencies. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. Lumped parameter equivalent circuits have also been developed to represent different isolation schemes in SPICE. The isolation characteristics of test structures employing the above techniques are computed using SPICE and the results compared with two-dimensional device simulation. The results are also compared with experimental measurements on actual silicon to validate the models.
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An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approache...
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An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed.
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A logic circuit is said to be combinational if the function it computes depends only on the inputs applied to the circuit, and is sequential if it depends on some past history in addition to the current inputs. Circuits that have ...
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A logic circuit is said to be combinational if the function it computes depends only on the inputs applied to the circuit, and is sequential if it depends on some past history in addition to the current inputs. Circuits that have an underlying topology that is acyclic are combinational, since feedback is a necessary condition for them to be sequential. However, it is not a sufficient condition since there exist combinational logic circuits that are cyclic. These occur often in bus structures in data paths. Traditional formal techniques in logic synthesis, logic analysis, and timing analysis of combinational circuits have restricted themselves to acyclic combinational circuits, since they have been unable to handle the analysis of circuits with cycles. Thus, in practice, these circuits are handled using clumsy work-arounds, which is obviously undesirable. This paper presents a formal analysis of these circuits and presents techniques for the logical and timing analysis of such circuits. These techniques are practically feasible on reasonably large circuits encountered in practice.
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Theoretically, normally-off silicon carbide (SiC) junction field-effect transistors (JFETs) do not require a negative gate voltage supply because they are in an off-state when the gate-source voltage is 0 V. However, most gate dri...
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Theoretically, normally-off silicon carbide (SiC) junction field-effect transistors (JFETs) do not require a negative gate voltage supply because they are in an off-state when the gate-source voltage is 0 V. However, most gate drivers for normally-off SiC JFETs require not only a positive power supply for turning on the JFET but also a negative power supply for turning it off and maintaining a negative gate-source voltage to suppress a false turn-on power loss caused by crosstalk during fast switching. Therefore, modifications of gate drivers increase complications and costs. In this study, a normally-off SiC JFET gate driver, which can be realized using a simple circuit configuration with a single power supply, is proposed. To minimize undesirable crosstalk, the gate-source voltage of the JFET is driven to a negative value and retained in the state for a long period of time. (c) 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.
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Quantum circuits are time-dependent diagrams describing the process of quantum computation. Usually, a quantum algorithm must be mapped into a quantum circuit. Optimal synthesis of quantum circuits is intractable, and heuristic me...
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Quantum circuits are time-dependent diagrams describing the process of quantum computation. Usually, a quantum algorithm must be mapped into a quantum circuit. Optimal synthesis of quantum circuits is intractable, and heuristic methods must be employed. With the use of heuristics, the optimality of circuits is no longer guaranteed. In this paper, we consider a local optimization technique based on templates to simplify and reduce the depth of nonoptimal quantum circuits. We present and analyze templates in the general case and provide particular details for the circuits composed of NOT, CNOT, and controlled-sqrt-of-NOT gates. We apply templates to optimize various common circuits implementing multiple control Toffoli gates and quantum Boolean arithmetic circuits. We also show how templates can be used to compact the number of levels of a quantum circuit. The runtime of our implementation is small, whereas the reduction in the number of quantum gates and number of levels is significant.
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An essentially nonlinear piezoelectric shunt circuit is proposed for the practical realization of nonlinear energy sink, and then applied to a mistuned bladed disk for blade vibration reduction. First, the global dynamics of a sin...
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An essentially nonlinear piezoelectric shunt circuit is proposed for the practical realization of nonlinear energy sink, and then applied to a mistuned bladed disk for blade vibration reduction. First, the global dynamics of a single degree-of-freedom linear mechanical oscillator, coupled to an essentially nonlinear shunted piezoelectric attachment, is studied. Under certain conditions, the nonlinear targeted energy transfer, i.e. a fast, passive energy transfer from the mechanical oscillator to the nonlinear attachment is observed. A numerical method, referred to as the variable-coefficient harmonic balance method, is developed to calculate quasi-periodic responses arising in the electromechanical system under harmonic forcing. Characterized by the nonexistence of a resonance frequency, the essentially nonlinear shunt circuit is able to work robustly over a broad frequency band with a smaller inductance requirement compared with the linear resonant shunt circuit. The application of piezoelectric shunt damping to simplified blade-disk structures is then taken into consideration. Shunted piezoelectrics are attached onto the disk surface in our damping strategy in order to reduce blade vibrations. Essential nonlinearity is also introduced into the piezoelectric shunted bladed disk system. Since the piezoelectric-based nonlinear energy sink is not a priori tuned to any specific frequency, a sound damping performance is achieved when blades become inevitably mistuned.
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