摘要 : The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with fi... 展开 The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5- mu m HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit*24-bit coefficient RAM, and a 256-bit*16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described. 收起