摘要 : Modern mobile processors integrating an increasing number of cores into one single chip demand large-capacity, on-chip, last-level caches (LLCs) in order to achieve scalable performance improvements. However, adopting traditional ... 展开
作者 | Jiang~ Lei Zhao~ Bo Yang~ Jun Zhang~ Youtao |
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作者单位 | |
期刊名称 | 《ACM Transactions on Design Automation of Electronic Systems 》 |
总页数 | 24 |
语种/中图分类号 | 英语 / TP39 |
关键词 | Design Performance Spin-transfer torque magnetic random access memory multilevel cell |
馆藏号 | N2008EPST0003915 |