摘要 : This paper presents an online offset-cancellation method which is embedding in a low-power 6-bit flash analog to digital converter. A set of low-offset comparators are employed as the first step and then utilizing a novel online m... 展开 This paper presents an online offset-cancellation method which is embedding in a low-power 6-bit flash analog to digital converter. A set of low-offset comparators are employed as the first step and then utilizing a novel online method leads to eliminate the effect of the relative offset between all comparators that is the origin of the bubble errors. The offset-cancellation mechanism is based on bulk-driven method where it takes about 0.7 mu s for the bulk nodes to settle down and cancel the relative offset voltage. Simulation results using HSPICE software with standard 0.18 mu m CMOS technology parameters, demonstrate 5.06 ENOB at 2GS/s with the power consumption of 35mW and 0.27FoM. 收起