摘要 : This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consu... 展开 This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies. 收起