摘要 : The capacitive coupling interference within floating-gate transistors is the main scaling barrier for highly dense nand Flash memories. In this case study, we propose a simulation-based methodology for the variability modeling, wh... 展开
作者 | Poliakov~ P. Blomme~ P. Pret~ A. V. Corbalan~ M. M. Gronheid~ R. Verkest~ D. Van Houdt~ J. Dehaene~ W. |
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作者单位 | |
期刊名称 | 《Electron Device Letters, IEEE》 |
页码/总页数 | p.164-166 / 3 |
语种/中图分类号 | 英语 / TN6 |
关键词 | Cell-to-cell interference line edge roughness (LER) nand Flash memory variability |
DOI | 10.1109/LED.2011.2176099 |
馆藏号 | IELEP0098 |