摘要 : After a brief discussion of previous work in the field of behavioral-to-structural translation, the bit-serial architecture which is the target of the bit-serial compiler is discussed. The bit-serial language (BSL) is then defined... 展开
| 作者 | Hartley~ R.I. Jasica~ J.R. |
|---|---|
| 期刊名称 | 《IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 》 |
| 页码/总页数 | P.877-886 / 10 |
| 语种/中图分类号 | 英语 / TN4 |
| 关键词 | Silicon compiler Signal processing algorithms Delay Circuits Very large scale integration Computer architecture Arithmetic Flow graphs Scheduling algorithm Linear programming |
| DOI | 10.1109/43.3219 |
| 馆藏号 | IELEP0072 |
