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The article is devoted to the study of how religious identity and belonging to a religious community of a resident of a megalopolis become a life strategy for overcoming loneliness, contribute to the development of an independent ...
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The article is devoted to the study of how religious identity and belonging to a religious community of a resident of a megalopolis become a life strategy for overcoming loneliness, contribute to the development of an independent life trajectory and the choice of stable value orientations. The text presents an analysis of the autobiographies of those who have chosen religious identity as their lifestyle strategy as a way of life and a way of self-determination. The methodological basis of the research is a combination of the theory of multiple modernities and the method of biographical interview.
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Provides a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
摘要 :
Provides a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
摘要 :
As the dimensions of middle-of-line (MOL) contacts shrink, the tungsten (W) gap-filling capability becomes more critical to eliminate function failure in SRAM and logic circuit caused by W-voids. The formation of W-voids is genera...
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As the dimensions of middle-of-line (MOL) contacts shrink, the tungsten (W) gap-filling capability becomes more critical to eliminate function failure in SRAM and logic circuit caused by W-voids. The formation of W-voids is generally related to contact profile, barrier (Ti/TiN) property and W-plug deposition method. The barrier layer may be degraded due to out-gassing from polymer residues underneath which prevent robust CVD W fill and leads to W void issue. In this paper, the impact of post-deposition plasma treatment of the underlying MOCVD-TiN barrier on the subsequent W gapfilling behavior and contact resistance was systematically investigated. Results show that the optimized plasma treatment of the barrier layer can reduce out-gassing during the subsequent W deposition, thus achieve better gapfilling capability and minize W-voids.
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摘要 :
As the dimensions of middle-of-line (MOL) contacts shrink, the tungsten (W) gap-filling capability becomes more critical to eliminate function failure in SRAM and logic circuit caused by W-voids. The formation of W-voids is genera...
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As the dimensions of middle-of-line (MOL) contacts shrink, the tungsten (W) gap-filling capability becomes more critical to eliminate function failure in SRAM and logic circuit caused by W-voids. The formation of W-voids is generally related to contact profile, barrier (Ti/TiN) property and W-plug deposition method. The barrier layer may be degraded due to out-gassing from polymer residues underneath which prevent robust CVD W fill and leads to W void issue. In this paper, the impact of post-deposition plasma treatment of the underlying MOCVD-TiN barrier on the subsequent W gapfilling behavior and contact resistance was systematically investigated. Results show that the optimized plasma treatment of the barrier layer can reduce out-gassing during the subsequent W deposition, thus achieve better gapfilling capability and minize W-voids.
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The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to h...
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The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to high-end servers. As designers continue to seek and evaluate low power technologies to enable the next generation of computing, the traditionally unheralded problem of voltage margin minimization has emerged to become one of the most significant sources of inefficiency and dissipation. Real-world integrated systems are margined, or guard-banded to address many sources of noise and variability including process, temperature, aging, and supply voltage noise and offsets. The trend toward multiple, fine-grained voltage domains, and aggressively voltage-scaled systems has exacerbated the problem. Voltage-margin minimization is a central component of modern low power design. Indeed, many recent low power efforts in the industry have moved beyond methodology and circuit design to address voltage margin minimization! In this tutorial, I propose a modern treatment of low-power design by actively managing supply-voltage variations. In contrast with text-book approaches, I examine a blend of well-established and emerging solutions that have proven to be effective in real-world constrained systems. The tutorial is organized in two parts. In the first, I begin by analyzing the main contributors toward voltage margins, including practical sources that are related to IC test and product deployment. A subsequent discussion on the major sources of voltage-margins is followed by an examination of a variety of circuit-architecture techniques used to directly and indirectly reduce voltage supply noise margins. High-density de-cap technology, active decap, supply-resonance avoidance, operation-throttling and adaptive clocking techniques to mitigate supply voltage noise. These techniques will be presented in the context of production designs and their constraints for a system-aware treatment of the subject. In the second section, I focus on Integrated Voltage Regulation (IVR) circuits. As designers grapple with more aggressive voltage scaling in the presence of supply variation, Integrated Voltage Regulation (IVR) has emerged as the key to achieving fine spatio-temporal control of SoC supply voltages. IVR has already been deployed for energy-efficient operation in high performance systems (Intel Haswell), and the trend to incorporate IVR to support finer voltage domains continues. We examine recent developments and challenges in the area of integrated voltage regulation across the three major voltage regulator technologies: switching-inductor converters, switched-capacitor converters, and low-dropout (linear) regulators. This tutorial provides an overview of low power circuit and architecture techniques with a system-level context. It is designed to be readily accessible to graduate students and practicing engineers alike, with a blend of well-established and emerging approaches to low power design.
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摘要 :
The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to h...
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The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to high-end servers. As designers continue to seek and evaluate low power technologies to enable the next generation of computing, the traditionally unheralded problem of voltage margin minimization has emerged to become one of the most significant sources of inefficiency and dissipation. Real-world integrated systems are margined, or guard-banded to address many sources of noise and variability including process, temperature, aging, and supply voltage noise and offsets. The trend toward multiple, fine-grained voltage domains, and aggressively voltage-scaled systems has exacerbated the problem. Voltage-margin minimization is a central component of modern low power design. Indeed, many recent low power efforts in the industry have moved beyond methodology and circuit design to address voltage margin minimization! In this tutorial, I propose a modern treatment of low-power design by actively managing supply-voltage variations. In contrast with text-book approaches, I examine a blend of well-established and emerging solutions that have proven to be effective in real-world constrained systems. The tutorial is organized in two parts. In the first, I begin by analyzing the main contributors toward voltage margins, including practical sources that are related to IC test and product deployment. A subsequent discussion on the major sources of voltage-margins is followed by an examination of a variety of circuit-architecture techniques used to directly and indirectly reduce voltage supply noise margins. High-density de-cap technology, active decap, supply-resonance avoidance, operation-throttling and adaptive clocking techniques to mitigate supply voltage noise. These techniques will be presented in the context of production designs and their constraints for a system-aware treatment of the subject. In the second section, I focus on Integrated Voltage Regulation (IVR) circuits. As designers grapple with more aggressive voltage scaling in the presence of supply variation, Integrated Voltage Regulation (IVR) has emerged as the key to achieving fine spatio-temporal control of SoC supply voltages. IVR has already been deployed for energy-efficient operation in high performance systems (Intel Haswell), and the trend to incorporate IVR to support finer voltage domains continues. We examine recent developments and challenges in the area of integrated voltage regulation across the three major voltage regulator technologies: switching-inductor converters, switched-capacitor converters, and low-dropout (linear) regulators. This tutorial provides an overview of low power circuit and architecture techniques with a system-level context. It is designed to be readily accessible to graduate students and practicing engineers alike, with a blend of well-established and emerging approaches to low power design.
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Summary form only given. Extensive developments are carried out in the fields of Applied Informatics. Among these fields, the fundamental problem is to develop the specific data processing and to provide each technology for the di...
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Summary form only given. Extensive developments are carried out in the fields of Applied Informatics. Among these fields, the fundamental problem is to develop the specific data processing and to provide each technology for the discipline of the Informatics. First, I would like to talk about an example of Neuro Informatics and Biomedical Informatics, which I was engaged in the research of the School of Medicine. In this talk, I will show the data processing problem in the experimental neurophysiology study and how to solve the problem in cooperation with Shannon information theory. Second, text classification problem in the Data Informatics is taken. In this discipline, since the text processing needs multiple distance measurements, the problem is how to cope with these situations for the higher classification accuracy. In the rough set theory, the data reduction is carried out by reducts, which have minimal discernibility classification ability. In this study, the multiple reducts corresponding to different distance measures are shown to be useful for the classification.
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Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
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