摘要 :
The undecidability of basic decision problems for general FIFO machines such as reachability and unboundedness is well-known. In this paper, we provide an underapproximation for the general model by considering only runs that are ...
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The undecidability of basic decision problems for general FIFO machines such as reachability and unboundedness is well-known. In this paper, we provide an underapproximation for the general model by considering only runs that are input-bounded (i.e. the sequence of messages sent through a particular channel belongs to a given bounded language). We prove, by reducing this model to a counter machine with restricted zero tests, that the rational-reachability problem (and by extension, control-state reachability, unboundedness, deadlock, etc.) is decidable. This class of machines subsumes input-letter-bounded machines, flat machines, linear FIFO nets, and monogeneous machines, for which some of these problems were already shown to be decidable. These theoretical results can form the foundations to build a tool to verify general FIFO machines based on the analysis of input-bounded machines.
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摘要 :
The undecidability of basic decision problems for general FIFO machines such as reachability and unboundedness is well-known. In this paper, we provide an underapproximation for the general model by considering only runs that are ...
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The undecidability of basic decision problems for general FIFO machines such as reachability and unboundedness is well-known. In this paper, we provide an underapproximation for the general model by considering only runs that are input-bounded (i.e. the sequence of messages sent through a particular channel belongs to a given bounded language). We prove, by reducing this model to a counter machine with restricted zero tests, that the rational-reachability problem (and by extension, control-state reachability, unboundedness, deadlock, etc.) is decidable. This class of machines subsumes input-letter-bounded machines, flat machines, linear FIFO nets, and monogeneous machines, for which some of these problems were already shown to be decidable. These theoretical results can form the foundations to build a tool to verify general FIFO machines based on the analysis of input-bounded machines.
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We show that for any r > 0, there is a network of First-In-First-Out servers and a fixed set of sessions such that: The network load is r with respect to the permanent sessions model with bounded arrivals. The network can be made unstable.
摘要 :
This study examines the effect on firm value of repealing the last-in, first-out (LIFO) inventory method for tax purposes. Our model extends prior literature by determining quantities and prices in equilibrium, rather than specify...
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This study examines the effect on firm value of repealing the last-in, first-out (LIFO) inventory method for tax purposes. Our model extends prior literature by determining quantities and prices in equilibrium, rather than specifying them exogenously. We find that LIFO repeal could increase the future after-tax cash flows of firms that had used LIFO, because the higher tax costs associated with FIFO result in lower equilibrium quantities and higher equilibrium output prices, which increase pretax cash flows. We illustrate our model by examining inventory methods used by firms in the oil industry.
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摘要 :
Due to having a direct affect for the growth of crops, the monitor and modification for the indicators of Greenhouse environment play significant roles in improving the yield of crops. The system, which adopts FPGA technology to c...
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Due to having a direct affect for the growth of crops, the monitor and modification for the indicators of Greenhouse environment play significant roles in improving the yield of crops. The system, which adopts FPGA technology to control and modify the air condition and lighting system by collecting and analyzing the data of the temperature and humidity, has achieved good effects in practice. In our study, the key technology of real-time data acquisition system based on FPGA is proposed. In particular, based on FPGA, the designed ADC0809 and asynchronous FIFO can save the data in real time, which can be analyzed and disposed timely, so that the environment can be corrected in time.
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