摘要 : Technology down scaling process divulges, the unveiled short channel effects (SCEs), which disrupts the behavior of bulk CMOS technology. In order to overcome these unveiled effects, the single gate controlling mechanism should be... 展开
作者 | Sreenivasa Rao Ijjada N. Anjani Devi T. Lokesh H. S. P. Tejomurthy |
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作者单位 | |
期刊名称 | 《Journal of computational and theoretical nanoscience》 |
总页数 | 6 |
语种/中图分类号 | 英语 / TB43 |
关键词 | Short Channel Effects TG-FinFET Capacitance Model Verilog-A Modeling |
馆藏号 | N2008EPST0009115 |