摘要 : In this research paper, a new Ⅲ/Ⅴ-Si-based TFET is proposed. This device benefits from a doping-less tunneling junction. By using a vertical structure, the issue of scaling is effectively addressed. Instead of using inductive me... 展开 In this research paper, a new Ⅲ/Ⅴ-Si-based TFET is proposed. This device benefits from a doping-less tunneling junction. By using a vertical structure, the issue of scaling is effectively addressed. Instead of using inductive metal, a cladding layer is utilized in our device, which turns the intrinsic source into a p~+ region. This helps to overcome the challenges related to silicide formation. We use the Silvaco ATLAS simulator to conduct all the numerical simulations. The impact of defect-related mechanisms on our device performance is thoroughly evaluated. We demonstrate that implementing a large underlap between the gate and drain region in a vertical configuration can effectively solve ambipolar conduction. Parameters such as I_(on) = 10.1 μA/μm, I_(on)/I_(off) = 1.1 × 10~(11), and f_r = 50.1 GHz at V_(GS) = 0.5V indicate that our device is an excellent option for low-power applications. 收起