摘要 : In this paper, work has been carried out for evaluation of drain current of TFET device with variation of different process parameters. We propose a double gate dual material TFET for which simulations show significant improvement... 展开 In this paper, work has been carried out for evaluation of drain current of TFET device with variation of different process parameters. We propose a double gate dual material TFET for which simulations show significant improvements in off current compared with conventional MOSFET devices. We present the variations of drain current with different parameters i.e., drain offset, work function, high-k dielectric to optimize our proposed device structure. The proposed TFET model is further used for SRAM Design. The read/write operations of TFET based SRAM cell are verified. In addition to these, Static Noise Margin (SNM) of TFET based SRAM cell also evaluated. The significant improvements in the results obtained validate our design approach and proposed TFET SRAM cell suitable for low power memory design. 收起