摘要 : In this paper, a thorough co-design procedure for the integrated PIN-diode limiter and low noise amplifier (LNA) is presented. A 27 GHz-35 GHz wideband integrated limiter low noise amplifier (limiter-LNA) is fabricated with the co... 展开 In this paper, a thorough co-design procedure for the integrated PIN-diode limiter and low noise amplifier (LNA) is presented. A 27 GHz-35 GHz wideband integrated limiter low noise amplifier (limiter-LNA) is fabricated with the combined PIN/0.15-μm-pHEMT technology for millimeter-wave radar applications. The PIN-diode limiter and the LNA are co-designed to improve the small signal performance. To improve the noise performance and the input-matching of the limiter-LNA, a novel limiter design method with the modified lossy TL model is presented. The measurement results illustrate that the small-signal gain is 20 ± 0.7 dB, the noise figure (NF) is 1.9 dB-2.4 dB, the output power at 1 dB compression point (OPldB) is larger than 12.1 dBm and the dc power consumption is only 96-mW. The limiter-LNA is capable of handling 38 dBm continuous wave (CW) input-power without failure. The chip area including testing pads is 2.3 mm × 1.0 mm. 收起