摘要 : This brief presents a sub-microwatt oversampling successive approximation register (SAR) analog-to-digital converter (ADC) dedicated to Internet of Things sensing applications. Several techniques are adopted in this design to enab... 展开 This brief presents a sub-microwatt oversampling successive approximation register (SAR) analog-to-digital converter (ADC) dedicated to Internet of Things sensing applications. Several techniques are adopted in this design to enable ultra-low power consumption while achieving 15-bit accuracy. The ground sampling technique minimizes DAC switching energy without requiring a common mode voltage while a comparator with dynamic bit trial settings achieves low noise in a power efficient manner using a two-stage dynamic preamplifier. Two redundant bits perform error correction, and dynamic element matching techniques are employed to enhance linearity. Implemented in a 180-nm CMOS technology, the proposed SAR ADC occupies an area of 0.22 mm(2). In the oversampling mode with 6.4-kHz sampling rate, it achieves a signal-to-noise-and-distortion ratio (SNDR) of 90 dB and a spurious-free dynamic range (SFDR) of 96 dB from dc to 200 Hz thanks to high-pass shaping of mismatch errors, and draws only 560 nA from a 1-V supply according to post-layout transient noise simulations, which is the first reported sub-microwatt ADC to exceed 90 dB of SNDR in the open literature. This translates to a Schreier figure-of-merit of 175.5 dB. In the low power Nyquist mode, it only consumes 41 nW at 400-Hz sampling rate and achieves an SNDR of 72 dB and an SFDR of 92 dB. 收起