摘要 : A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter is presented. This adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm... 展开 A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter is presented. This adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm2. The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. 收起