摘要 : Impact of strained silicon effects in double-gated FinFET structures on static random access memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) SRAM cell embodiments representing unstrained, str... 展开 Impact of strained silicon effects in double-gated FinFET structures on static random access memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) SRAM cell embodiments representing unstrained, strained, and NFET-only-strained devices are compared against a planar PDSOI SRAM cell design. The metrics encompass both static and dynamic behavior of the cell and are analyzed through 2-D process hardware-calibrated device models <formula formulatype="inline"><tex Notation="TeX">$(L_{g}=25~{rm nm})$</tex></formula>. The key findings of this letter are: 1) PFET devices with tensile strain are found to degrade the FinFET cell Read Noise Margin and cell ability to write a strong “1”; 2) by restricting the tensile strain to the NFET devices FinFET SRAM cell Read stability and access times improve by 10%–20% relative to their unstrained FinFET and NFET-only strained PDSOI counterparts. 收起