摘要 : A design approach and accurate modeling techniques developed to realize a GaAs monolithic, 6-GHz, two-stage, low-noise amplifier (LNA) with a measured 1.7 dB noise figure and associated 21 dB gain are discussed. This self-biased L... 展开 A design approach and accurate modeling techniques developed to realize a GaAs monolithic, 6-GHz, two-stage, low-noise amplifier (LNA) with a measured 1.7 dB noise figure and associated 21 dB gain are discussed. This self-biased LNA design, with chip dimensions of 80 mil*135 mil, utilizes an ion-implantation FET model which predicts measured in-band amplifier gain to within 0.5 dB and peak frequency response to within 4%. The derived noise parameter estimation process, which uses a Gaussian elimination technique to predict the measured noise figure to within 0.2 dB, reduces a set of complex, binomial equations to simple relationships which are easily programmable. A deep-recessed gate realization of this LNA design demonstrates that LNA low-noise performance is achievable under FET saturated drain current conditions. 收起