摘要 : A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is ... 展开
作者 | Narain D. Arora Li Song |
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期刊名称 | 《IEEE Electron Device Letters》 |
页码/总页数 | p.92-94 / 3 |
语种/中图分类号 | 英语 / TN10 |
关键词 | Capacitance modeling Current measurement On-chip capacitance Very large-scale integration (VLSI) interconnect |
馆藏号 | 4-2908-15a |