摘要 :
A new functional semantics is proposed for synchronous circuits, as a basis for reasoning formally about that class of hardware systems. Technically, we define an extensional semantics with monotonic length-preserving functions on...
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A new functional semantics is proposed for synchronous circuits, as a basis for reasoning formally about that class of hardware systems. Technically, we define an extensional semantics with monotonic length-preserving functions on finite strings, and an intensional semantics based on functionals on those functions. As support for the semantics we prove the equivalence of the extensional semantics with a simple operational semantics, as well as a characterization of circuits which obey the every loop is clocked design rule. Also, we develop the foundations in complete detail both to increase confidence in the theory, and as a prerequisite to its future mechanization. (rrh)
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摘要 :
A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and pass...
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A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.
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摘要 :
An open loop digital frequency multiplier is described which has a multiplied output synchronized to low frequency clock pulse. The system includes a multistage digital counter which provides a pulse output as a function of an int...
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An open loop digital frequency multiplier is described which has a multiplied output synchronized to low frequency clock pulse. The system includes a multistage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one shot multivibrator which, in turn, is driven by a reference frequency input.
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