摘要: An open loop digital frequency multiplier is described which has a multiplied output synchronized to low frequency clock pulse. The system includes a multistage digital counter which provides a pulse output as a function of an int... 展开 An open loop digital frequency multiplier is described which has a multiplied output synchronized to low frequency clock pulse. The system includes a multistage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one shot multivibrator which, in turn, is driven by a reference frequency input. 收起