摘要 :
The AMPLEX chip is an AMPlifying multipLEXing, CMOS technology device. It is an analog signal processor, designed at CERN for use with silicon microstrip detectors. However, its application is not limited to conventional microstri...
展开
The AMPLEX chip is an AMPlifying multipLEXing, CMOS technology device. It is an analog signal processor, designed at CERN for use with silicon microstrip detectors. However, its application is not limited to conventional microstrips and it is being used in various detector systems. AMPLEX design goals included modest power consumption and reasonable speed. The main drawback of the chip seems to be a lack of documentation. This report will attempt to fill this void by providing a summary of the properties of the AMPLEX chip, a brief synopsis of how it functions, and most importantly an explanation of how to make it operate in a practical circuit. The information in this paper pertains to the application of the AMPLEX chip to microstrip detectors for the electron beam at Brookhaven National Laboratory's Accelerator Test Facility. Detector design was carried out in the Instrumentation Division. Details of the driving circuit and some information on the inner workings of the AMPLEX chip came directly from CERN and from the paper by E. Beuville et al. The author is in no way connected with CERN, nor is he attempting to promote the AMPLEX chip; he is merely interested in making the chip work and in making it easier for others who might wish the same. Some knowledge of the interior of the chip will help in understanding the process of amplifying and shaping signals, so that is where this paper begins.
收起
摘要 :
This report describes the design and fabrication of an audio output amplifier built with a Master-Slice integrated circuit. The purpose of this program was the development of a general-purpose communication circuit that would demo...
展开
This report describes the design and fabrication of an audio output amplifier built with a Master-Slice integrated circuit. The purpose of this program was the development of a general-purpose communication circuit that would demonstrate the utility of the Master Slice, and also serve as a means of familiarizing NELC personnel with assembly techniques associated with this technology. For detailed information concerning the Master Slice IC, the reader should refer to ARINC Research Publications W7-425-TN001-1, April 1967; W7-426-TN001-1, August 1967; and W8-447-TN001-1, March 1968.
收起
摘要 :
The goal of the work was to investigate new cell structures for dense integration211 of Cellular Nonlinear Network Universal Machine (CNNUM). The final objective was 211 to design and realize a Universal Machine chip with a large ...
展开
The goal of the work was to investigate new cell structures for dense integration211 of Cellular Nonlinear Network Universal Machine (CNNUM). The final objective was 211 to design and realize a Universal Machine chip with a large amount of cells in 211 the cell grid. With this design the real potential of the CNNUM for very fast 211 information processing was to be demonstrated.
收起
摘要 :
At Fermilab, both pixel detector multichip module and sensor hybridization arebeing developed for the BTeV experiment.The BTeV pixel detector is based on a design relying on a hybrid approach. With this approach, the readout chip ...
展开
At Fermilab, both pixel detector multichip module and sensor hybridization arebeing developed for the BTeV experiment.The BTeV pixel detector is based on a design relying on a hybrid approach. With this approach, the readout chip and the sensor array are developed separately and the detector is constructed by flip-chip mating the two together.This paper presents strategies to handle the required data rate and perormance results of the first prototype and detector hybridization.
收起
摘要 :
The Commissioninstituted this investigation on January 4, 2011, based on a complaint filed by Rambus Inc. of Sunnyvale, California (Rambus), alleging a violation of section 337 in the importation, sale for importation, and sale Wi...
展开
The Commissioninstituted this investigation on January 4, 2011, based on a complaint filed by Rambus Inc. of Sunnyvale, California (Rambus), alleging a violation of section 337 in the importation, sale for importation, and sale Withinthe United States after importation of certain semiconductor chips and products containing the same. 76 Fed. Reg. 384 (Jan. 4, 2011). The complaint alleged the infringement of various claims of patents including U.S. Patent Nos. 6,470,405; 6,591,353; 7,287,109 (collectively, the Barth patents); and Nos. 7,602,857; and 7,715,494 (collectively, the Dally patents). The Barth patents share a common specification, as do the Dally patents.
收起
摘要 :
According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first k...
展开
According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2 or more, 5 or more, 10 or more, 20 or more, 30 or more, or 40 or more.
收起
摘要 :
High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pi...
展开
High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pixel detectors (arrays of silicon diodes bump bonded to arrays of front-end electronic cells) is the state of the art technology able to meet these challenges. We report on irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. Prototype pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 micron CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 87 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been extensively measured.
收起
摘要 :
A neural network circuit structure was previously proposed for making an isolated electron trigger for the CDF plug calorimeter. Here we discuss a study of the isolation performance of the Intel ETANN (Electrically Trainable Analo...
展开
A neural network circuit structure was previously proposed for making an isolated electron trigger for the CDF plug calorimeter. Here we discuss a study of the isolation performance of the Intel ETANN (Electrically Trainable Analog Neural Network) chip. We used the PC based ETANN development system and Monte Carlo generated shower patterns to test the chip. A C ++ application program was developed that runs within the development system but extends chip control and testing capabilities beyond the standard routines. With this program several configurations of the chip parameters were tested and the results are discussed here.
收起
摘要 :
We report test results for the second version of the current-splitter chip for the Photo Multiplier Tube (PMT) digital readout system. The chip was designed by Fermilab and fabricated using the Orbit 2 micron BiCMOS process. Versi...
展开
We report test results for the second version of the current-splitter chip for the Photo Multiplier Tube (PMT) digital readout system. The chip was designed by Fermilab and fabricated using the Orbit 2 micron BiCMOS process. Version 2 of the splitter has 10 splitting ranges compared to 9 in the previous design. Measurements were done to test the performance of the current-splitter chip at the Physics Research Division, Superconducting Super Collider Laboratory (SSCL).
收起
