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This paper presents design and implementation of a framework for high-level synthesis (HLS), which allows easy description and acceleration of stencil computation with building-cube method (BCM) on FPGAs. The BCM is one of adaptiv...
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This paper presents design and implementation of a framework for high-level synthesis (HLS), which allows easy description and acceleration of stencil computation with building-cube method (BCM) on FPGAs. The BCM is one of adaptive mesh refinement methods, which can reduce computational costs by using various granularity of cubes depending on computational precision required by target models. By placing some restrictions on size ratios between adjacent cubes, the BCM offers affinity to parallel processing. However, non-continuous memory access imposed by the irregular cubes does not straightforwardly match with stream processing on FPGA accelerators. To fill this gap, we design and implement a BCM framework as a class library on a high-level synthesis environment. The framework automatically generates mechanisms required for the BCM, such as reordering modules of data streams and data interpolation hardware between different cubes. The proposed framework is evaluated in terms of computing performance, memory performance and required hardware resources on a Maxeler Technologies FPGA accelerator. The results reveal that a performance overhead of data exchange between different sizes of cubes is reasonably small.
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In this paper, we propose a Localized Feature Selection (LFS) framework tailored to the HL-SOT approach to sentiment analysis. Within the proposed LFS framework, each node classifier of the HL-SOT approach is able to perform class...
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In this paper, we propose a Localized Feature Selection (LFS) framework tailored to the HL-SOT approach to sentiment analysis. Within the proposed LFS framework, each node classifier of the HL-SOT approach is able to perform classification on target texts in a locally customized index term space. Extensive empirical analysis against a human-labeled data set demonstrates that with the proposed LFS framework the classification performance of the HL-SOT approach is enhanced with computational efficiency being greatly gained. To find the best feature selection algorithm that caters to the proposed LFS framework, five classic feature selection algorithms are comparatively studied, which indicates that the TS, DF, and MI algorithms achieve generally better performances than the CHI and IG algorithms. Among the five studied algorithms, the TS algorithm is best to be employed by the proposed LFS framework.
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During the phase II of the LHC physics program, called High Luminosity LHC (HL-LHC), the accelerator will increase the instantaneous luminosity up to 5×10~(34)cm~(-2) s~(-1). At HL-LHC, the CMS Resistive Plate Chambers (RPC) syst...
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During the phase II of the LHC physics program, called High Luminosity LHC (HL-LHC), the accelerator will increase the instantaneous luminosity up to 5×10~(34)cm~(-2) s~(-1). At HL-LHC, the CMS Resistive Plate Chambers (RPC) system will be subjected to high background radiations which could induce non-recoverable aging effects and can alter the detector properties. A new longevity test is then needed to estimate the impact of HL-LHC conditions up to an integrated charge equivalent to the integrated luminosity of 3000 fb~(-1), to confirm that the RPC system will survive the harsher background conditions. A dedicated consolidation program is ongoing at the CERN Gamma Irradiation Facility (GIF++), where a few RPC detectors are exposed to intense gamma radiation. The main detector parameters (currents, rate, and resistivity) are under monitoring as a function of the integrated charge and the performance studied with a muon beam. After having collected a significant amount of the total irradiation, preliminary results will be presented.
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This paper describes the integration structures for the silicon strips tracker of the ATLAS detector for the Phase-II upgrade of the Large Hadron Collider (LHC), also referred to as High-Luminosity LHC (HL-LHC). Silicon strip sens...
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This paper describes the integration structures for the silicon strips tracker of the ATLAS detector for the Phase-II upgrade of the Large Hadron Collider (LHC), also referred to as High-Luminosity LHC (HL-LHC). Silicon strip sensors are arranged in highly modular structures, called 'staves' and 'petals'. This paper focuses on the prototyping effort developed by the strips tracker barrel community, as well as on the description of one of the latest stave prototypes. This new prototype is composed of a particular core structure, in which a shield-less bus tape is embedded in between carbon fiber lay-ups. Electrical and thermal performances of the prototype are presented, as well as a description of the assembly procedures and tools.
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ALICE is the experiment dedicated to the study of the quark gluon plasma in heavy-ion collisions at the CERN LHC. Improvements of the ALICE detectors are envisaged for the upgrade of HL-LHC in year 2018. In particular, in forward ...
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ALICE is the experiment dedicated to the study of the quark gluon plasma in heavy-ion collisions at the CERN LHC. Improvements of the ALICE detectors are envisaged for the upgrade of HL-LHC in year 2018. In particular, in forward region, the Muon Forward Tracker (MFT) is a proposal of a new tracking device, to be added in complement with the current Muon Spectrometer. The main motivations are to overcome the intrinsic limitations of the present Muon Spectrometer, almost blind to the details of the vertex region because of the Hadronic Absorber thickness, and to perform new measurements of general interest for the whole ALICE physics. This paper presents the conceptual design of the MFT [1], focusing particularly on the chosen technology for the tracker. After a short presentation of the pixel sensor architecture, a summary of the in-lab tests results of the first sensor prototype are presented. Concept for the data acquisition system is also discussed. Finally, preliminary thermal simulations and support structure concept is reported.
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Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath co...
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Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction, too.
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摘要 :
Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath co...
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Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction, too.
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摘要 :
Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath co...
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Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction. too.
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The readout electronics of the ATLAS Hadronic Endcap Calorimeter will have to withstand the about ten times larger radiation environment of the future high-luminosity LHC (HL-LHC) compared to their design values. The GaAs ASIC whi...
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The readout electronics of the ATLAS Hadronic Endcap Calorimeter will have to withstand the about ten times larger radiation environment of the future high-luminosity LHC (HL-LHC) compared to their design values. The GaAs ASIC which comprises the heart of the readout electronics has been exposed to neutron and proton radiation with fluences up to ten times the total expected fluences for ten years of running of the HL-LHC. Neutron tests were performed at the NPI in ?e?, Czech Republic, where a 36 MeV proton beam is directed on a thick heavy water target to produce neutrons. The proton irradiation was done with 200 MeV protons at the PROSCAN area of the Proton Irradiation Facility at the PSI in Villigen, Switzerland. In-situ measurements of S-parameters in both tests allow the evaluation of frequency dependent performance parameters - like gain and input impedance - as a function of the fluence. The linearity of the ASIC response has been measured directly in the neutron tests with a triangular input pulse of varying amplitude. The performance measurements and expected performance degradations under HL-LHC conditions are presented.
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Cytochrome P450 4F3 (CYP4F3) catalyzes the inactivation of leukotriene B4 by (c)-oxidation in human neutrophils. Here, we examined the mRNA and protein expression of the CYP4F3 in HL-60 cells, an acute promyelocytic leukemia cell ...
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Cytochrome P450 4F3 (CYP4F3) catalyzes the inactivation of leukotriene B4 by (c)-oxidation in human neutrophils. Here, we examined the mRNA and protein expression of the CYP4F3 in HL-60 cells, an acute promyelocytic leukemia cell line, in the presence of hydroquinone(HQ). We found hydroquinone led to a decrease in cell proliferation and a increase in cell apoptosis in a dose-dependent and time-dependent manner, it also most strongly induced the expression of the CYP4F3. CYP4F3 appears to be responsible for the cell proliferation and cell apoptosis, which may be play a role in the toxicity of hydroquinone.
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