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It is commonly stated that a directory-based coherence protocol is the design of choice to provide maximum performance in coherence maintenance for shared-memory many-core CMPs. Nevertheless, new solutions are emerging to achieve ...
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It is commonly stated that a directory-based coherence protocol is the design of choice to provide maximum performance in coherence maintenance for shared-memory many-core CMPs. Nevertheless, new solutions are emerging to achieve acceptable levels of on-chip area overhead and energy consumption to also meet scalability. In this work, we propose the Express COherence NOtification (ECONO) protocol, a coherence protocol aimed at providing high performance with minimal on-chip area and energy consumption for superior scalability. To maintain coherence, ECONO relies on express coherence notifications which are broadcast atomically over a dedicated lightweight and power-efficient on-chip network leveraging state-of-the-art technology. We implement and evaluate ECONO utilizing full-system simulation, a representative set of benchmarks, and compare it against two contemporary coherence protocols: Hammer and Directory. While ECONO achieves slightly better performance than Directory, our proposal does not need to encode sharer sets like in Hammer, saving significant on-chip area and energy even when considering the extra hardware resources required by ECONO. Projections for a 1024-core CMP reveal that, in comparison to one of the most scalable directory-based protocols to date, ECONO entails more than 2x less on-chip storage overhead while keeping with reasonable power dissipation.
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TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonde...
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TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≦50μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.
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摘要 :
TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonde...
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TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≦50μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.
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This paper aims to enhance the Electro-Kinetic Force Assisted Chemical Mechanical Planarization (EKF-CMP) process with a modularized electrode design to generate electro-osmosis flow of slurry circulation for improving the removal...
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This paper aims to enhance the Electro-Kinetic Force Assisted Chemical Mechanical Planarization (EKF-CMP) process with a modularized electrode design to generate electro-osmosis flow of slurry circulation for improving the removal rate of trench-silicon-via, TSV Cu-CMP. Experimental test of TSV-CMP with copper blanket wafer and pattern substrates have been performed and investigated. Results have shown that EKF-CMP can achieve material removal rate (MRR) up to 24.19% of blanket Cu-CMP as compared with the conventional CMP. For TSV patterned Cu-CMP, dishing can be reduced by 29.7% compared with conventional CMP. Finally, the EKF-CMP has been verified to improve the MRR and also reducing the dishing of TSV-CMP with this modularized electrode design. Results of such EKF-CMP can be applied on integration devices for hybrid IC demands.
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In chemical mechanical planarization (CMP) processes, ceria is generally used as the abrasive. After the CMP process, many ceria particles adhere to the wafer surface and must be removed prior to subsequent processing. In this stu...
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In chemical mechanical planarization (CMP) processes, ceria is generally used as the abrasive. After the CMP process, many ceria particles adhere to the wafer surface and must be removed prior to subsequent processing. In this study, the effect of varied viscosity was investigated during the buffing CMP process for ceria particle removal. After contaminating the wafer surface with ceria slurry, the ceria particles were removed through the buffing CMP process. The wafer surface was analyzed through inductively coupled plasma mass spectrometry (ICP-MS) to confirm cleaning efficiency. The ICP-MS data showed that, as buffing CMP solution viscosity increased, cleaning efficiency improved. These results suggest that increasing the viscosity of the buffing CMP solution improves its effectiveness in removing ceria particles.
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摘要 :
In chemical mechanical planarization (CMP) processes, ceria is generally used as the abrasive. After the CMP process, many ceria particles adhere to the wafer surface and must be removed prior to subsequent processing. In this stu...
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In chemical mechanical planarization (CMP) processes, ceria is generally used as the abrasive. After the CMP process, many ceria particles adhere to the wafer surface and must be removed prior to subsequent processing. In this study, the effect of varied viscosity was investigated during the buffing CMP process for ceria particle removal. After contaminating the wafer surface with ceria slurry, the ceria particles were removed through the buffing CMP process. The wafer surface was analyzed through inductively coupled plasma mass spectrometry (ICP-MS) to confirm cleaning efficiency. The ICP-MS data showed that, as buffing CMP solution viscosity increased, cleaning efficiency improved. These results suggest that increasing the viscosity of the buffing CMP solution improves its effectiveness in removing ceria particles.
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We present the chip-scale CMP simulator for layer uniformity analysis within Calibre DFM framework. The CMP simulator is intended to be used during smart fill optimizations, accurate parasitic extractions, defocus variability comp...
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We present the chip-scale CMP simulator for layer uniformity analysis within Calibre DFM framework. The CMP simulator is intended to be used during smart fill optimizations, accurate parasitic extractions, defocus variability compensations, and other DFM applications. It is tightly integrated with Mentor Graphics DFM components for yield analysis and optimization. The paper discusses the key concepts of the electro-chemical copper deposition and slurry CMP models that are used in the simulation. The data flow is described, including the use of mask information from design layout data. Application examples, including the process flow and the simulated results, are presented. Both the electroplating and the CMP models include empirical parameters that describe the width- and space- dependency. Fast and accurate global optimization search algorithms are implemented to find optimum modeling parameter values.
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We present the chip-scale CMP simulator for layer uniformity analysis within Calibre DFM framework. The CMP simulator is intended to be used during smart fill optimizations, accurate parasitic extractions, defocus variability comp...
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We present the chip-scale CMP simulator for layer uniformity analysis within Calibre DFM framework. The CMP simulator is intended to be used during smart fill optimizations, accurate parasitic extractions, defocus variability compensations, and other DFM applications. It is tightly integrated with Mentor Graphics DFM components for yield analysis and optimization. The paper discusses the key concepts of the electro-chemical copper deposition and slurry CMP models that are used in the simulation. The data flow is described, including the use of mask information from design layout data. Application examples, including the process flow and the simulated results, are presented. Both the electroplating and the CMP models include empirical parameters that describe the width- and space- dependency. Fast and accurate global optimization search algorithms are implemented to find optimum modeling parameter values.
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Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and perfor...
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Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer's total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMP Analyzer to improve Design-for-Manufacturability (DFM) robustness.
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摘要 :
Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and perfor...
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Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer's total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMP Analyzer to improve Design-for-Manufacturability (DFM) robustness.
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