摘要 :
The DNA damage response (DDR) is a crucial signaling network that preserves the integrity of the genome. This network is an ensemble of distinct but often overlapping subnetworks, where different components fulfill distinct functi...
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The DNA damage response (DDR) is a crucial signaling network that preserves the integrity of the genome. This network is an ensemble of distinct but often overlapping subnetworks, where different components fulfill distinct functions in precise spatial and temporal scenarios. To understand how these elements have been assembled together in humans, we performed comparative genomic analyses in 47 selected species to trace back their emergence using systematic phylogenetic analyses and estimated gene ages. The emergence of the contribution of posttranslational modifications to the complex regulation of DDR was also investigated. This is the first time a systematic analysis has focused on the evolution of DDR subnetworks as a whole. Our results indicate that a DDR core, mostly constructed around metabolic activities, appeared soon after the emergence of eukaryotes, and that additional regulatory capacities appeared later through complex evolutionary process. Potential key posttranslational modifications were also in place then, with interacting pairs preferentially appearing at the same evolutionary time, although modifications often led to the subsequent acquisition of new targets afterwards. We also found extensive gene loss in essential modules of the regulatory network in fungi, plants, and arthropods, important for their validation as model organisms for DDR studies.
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Novel dasatinib analogues as DDR1 and DDR2 inhibitors were designed and synthesized. The synthesized compounds were screened for DDR1 and DDR2 kinase inhibitory and cancer cell proliferation inhibitory activities. Some of the comp...
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Novel dasatinib analogues as DDR1 and DDR2 inhibitors were designed and synthesized. The synthesized compounds were screened for DDR1 and DDR2 kinase inhibitory and cancer cell proliferation inhibitory activities. Some of the compounds showed the potent inhibitory activities against both DDR1 and DDR2, as well as anticancer activity in low nanomolar range against K562 cell line; especially, compound 3j demonstrated significantly better inhibitory potency than the parental dasatinib against both DDRs and also demonstrated the potent inhibitory activity against K562 cell lines (IC50 values of 2.26 +/- 0.46 nm for DDR1, 7.04 +/- 2.90 nm for DDR2, and 0.125 +/- 0.017 nm for K562 cell line).
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Cancer is the 2(nd) most fatal disease around the globe. Various receptors have been showed to be overexpressed and/or mutated in numerous cancers. Discoidin domain receptors 1 (DDR1) and 2 (DDR2) are one of the novel receptor tyr...
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Cancer is the 2(nd) most fatal disease around the globe. Various receptors have been showed to be overexpressed and/or mutated in numerous cancers. Discoidin domain receptors 1 (DDR1) and 2 (DDR2) are one of the novel receptor tyrosine kinases (RTKs), which have been proved to regulate various cellular signaling pathways, cell proliferation, adhesion, migration, matrix remodeling, and dysregulation of these receptors may lead to metastatic cancer progressions. These receptors belong to unique category of RTKs, which require collagen binding for its activation. Yet the mechanism of this extracellular collagen binding and activation of cytosolic kinase domain of the receptors is not clear. Like other RTKs, these receptors also showed its extensive implications in numerous cancers like lung, breast, ovarian, pancreatic cancer and many others. Therefore DDR1 and DDR2 emerge as potential therapeutic targets in preventing cancer. Various small molecule tyrosine kinase inhibitors have been developed against these two receptors and proved to be highly efficacious in reducing tumor progressions. This review would highlight the detailed structure, functions, mechanism of action, signaling pathways of DDR1 and DDR2, their roles in cancer developments and the inhibition of these receptors with numerous inhibitors can be a promising strategy to combat this hefty menace.
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This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tra...
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This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65-7.0 GHz and occupies an area of only 0.021 mm(2). The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p-p) jitter of the output clock is about 4.55 ps at 7 GHz.
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This paper presents two new all-digital phase inversion delay-locked loop (PIDLL) architectures for high-speed DRAMs. The proposed PIDLLs utilize a new phase inversion scheme to reduce the total number of delay elements in the dig...
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This paper presents two new all-digital phase inversion delay-locked loop (PIDLL) architectures for high-speed DRAMs. The proposed PIDLLs utilize a new phase inversion scheme to reduce the total number of delay elements in the digitally controlled delay line by approximately one-half, enabling shorter locking time, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. A new area-efficient digital feedback delay element is proposed to achieve high delay resolution and linear delay characteristics. To verify the proposed PIDLL architecture, two PIDLL chips were fabricated and measured. The first PIDLL is fabricated in a 0.13-mu m 1.2-V CMOS process and operates over a frequency range of 0.1-1.5 GHz. Using a variable SAR-based hybrid search algorithm, the first chip achieves fast locking time of less than 38 clock cycles and dissipates the power of 5.9 mW from at 1 GHz and exhibits a measured peak-to-peak (p-p) output clock jitter of 11.25 ps at 1.5 GHz. The second PIDLL is fabricated in a 65-nm 1.0-V CMOS process, occupies an area of only 0.015 mm(2), and operates over a frequency range of 1.5-5.0 GHz. The second PIDLL achieves a p-p output clock jitter of 12.3 ps and dissipates the power of 6.6 mW at 5 GHz.
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