摘要 : In this paper, we present an efficient hardware architecture of bitplane coding in VC-1. Bitplane coding has demerit of implementation area because bitplane coding supports seven different decoding modes. Also, particular mode con... 展开 In this paper, we present an efficient hardware architecture of bitplane coding in VC-1. Bitplane coding has demerit of implementation area because bitplane coding supports seven different decoding modes. Also, particular mode consumes many clock cycles. In order to reduce the area, we use suitable register banks that different modes share for decoding and use two SRAMs that are shared for different frames. Also, we designed MODE2 and DIFF modules with high-performance capability to account for the intensive processing that Differential-2 mode undergoes. The hardware implementation, based on 0.065-μm standard cell library, consumes only 19.52K (excluding two 135 × 40 SRAMs) gates at a clock frequency of 133 MHz. Our architecture supports real-time bitplane coding for high-resolution (1280 × 720) video at 30 fps. 收起