摘要 : The demand for the high-speed PLL has increased to fulfil the requirement of the present RF communication industry. This paper deals with the designing of a third-order G(m)-C loop filter with improved PLL performance. The high ga... 展开 The demand for the high-speed PLL has increased to fulfil the requirement of the present RF communication industry. This paper deals with the designing of a third-order G(m)-C loop filter with improved PLL performance. The high gain and low power Operational transconductance amplifier (OTA) is the basic building block of the third order G(m)-C filter. The proposed folded cascode (FC) OTA has designed using dynamic threshold MOS (DTMOS) type input differential stage to achieve the dc gain of 77.07 dB, UGB of 25.02 MHz and power consumption of 94.89 mu W. The low power FC OTA design leads to the enhancement in the figure of merits for FOMS and FOML for the small-signal and large-signal operation that is given 4777.07 MHz.pF/mW and 3891.91 V.pF/mu s.mW, respectively. Further, the third-order reconfigurable G(m)-C filter has designed and achieved 25.02 MHz of the cut-off frequency. It consumes power of 283.66 mu W at 1.8 V supply voltage that shows 8.44 % reduction in power as compared to state of the art work. The proposed G(m)-C is attained --132.08 dBc/Hz phase noise at 1MHz offset that shows 21.62 dB reduction in the phase noise than the reported results. The locking time of approximately 0.34 mu s has measured with the help of an analytical approach for the Integer-N PLL 5G applications. The transistor-level simulation has been done using 180 nm CMOS process. 收起