摘要 : The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exace... 展开 The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exacerbated variability are the major concerns of sub threshold circuits. Furthermore, the global interconnects significantly affects the performance and power dissipation in sub threshold circuits. The obvious reason is the increased capacitance of long global interconnects which is further augmented with increase in sub threshold CMOS driver resistance. This paper explores the performance of sub threshold global interconnect with six different configurations of DG FinFET driver circuit viz. FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG. Performance analysis indicates that FinFET SG configuration exhibits 60.7, 0.8, 2.3, 37 and 40% better energy efficiency compared to TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG respectively at 225 mV supply voltage. Furthermore, the crosstalk analysis results shows that the glitch amplitude in TGSG driven interconnect and THYBRID driven interconnect is increased by 89.6 and 74% respectively compared to FinFET SG driven interconnect. This work also investigates the suitability of conventional buffer insertion technique for enhancing the performance of DG FinFET driven sub threshold global interconnects. The buffered and un-buffered interconnect shows comparable delay, PDP and EDP in sub threshold region. Furthermore, Monte Carlo analysis results indicate that spread in delay exhibited by FinFET SG driven un-buffered interconnect circuit is lesser by 25% compared to FinFET SG driven buffered circuit in sub threshold region. 收起