摘要: The objective of this 18-month exploratory development effort was the fabrication and testing of the Programmable Image Processing Element (PIPE) Large-Scale Integrated Circuits developed under the Phase I contract and the design ... 展开 The objective of this 18-month exploratory development effort was the fabrication and testing of the Programmable Image Processing Element (PIPE) Large-Scale Integrated Circuits developed under the Phase I contract and the design and fabrications of a brassboard to demonstrate the versality of the PIPE LSIC. Two phases of IC processing were required because minor layout errors were discovered in the first-pass ICs, and the redesign, photomask generation, processing, and testing steps were repeated. The second-pass ICs were 100-percent functional and packaged in 64-pin dual in-line packages (DIPs) for use in the brassboard. A flexible brassboard operating in or near real-time was developed to demonstrate the PIPE LSIC. Although simple, the brassboard operates the PIPE LSIC in both its serial and parallel modes and demonstrates its processing of vector/transforms and neighborhood operators. Images composed of 512 by 512 8-bit pixels are formed in a frame buffer and processed at frame rates determined by the PIPE LSIC throughput, buffer memory speed, brassboard architecture, and the algorithm being computed. Eight PIPE LSICs are used in the brassboard. For the 3 X 3 differential edge detectors, four PIPE LSICs calculate the horizontal response while the other four PIPE LSICs calculate the vertical response. (Author) 收起