摘要 : We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, w... 展开
作者 | Nakai~ S. Miyazaki~ Y. Yasuda~ M. |
---|---|
作者单位 | |
期刊名称 | 《Semiconductor Manufacturing, IEEE Transactions on》 |
页码/总页数 | p.317-322 / 6 |
语种 | 英语 |
关键词 | Failure analysis SRAM chips integrated circuit layout |
DOI | 10.1109/TSM.2012.2202769 |
馆藏号 | IELEP0231 |