摘要 : The organization and circuit design of a 1.0 GHz integer processorbuilt in 0.25 Μm CMOS technology are presented, a microarchitectureemphasizing parallel computation with a single late select per cycle,structured control logic imp... 展开 The organization and circuit design of a 1.0 GHz integer processorbuilt in 0.25 Μm CMOS technology are presented, a microarchitectureemphasizing parallel computation with a single late select per cycle,structured control logic implemented by read-only-memories andprogrammable logic arrays, and a delayed reset dynamic circuit styleenabling complex functions to be implemented in a few levels of logicare among the key design choices described. A means for at-speed scantesting of this high-frequency processor by a low-speed tester is alsopresented 收起