摘要 : In this paper, we present an approach for applying two supplyvoltages to optimize power in CMOS digital circuits under the timingconstraints. Given a technology-mapped network, we first analyze thepower/delay model and the timing ... 展开 In this paper, we present an approach for applying two supplyvoltages to optimize power in CMOS digital circuits under the timingconstraints. Given a technology-mapped network, we first analyze thepower/delay model and the timing slack distribution in the network. Thena new strategy is developed for timing-constrained optimization issuesby making full use of stacks. Based on this strategy, the powerreduction is translated into the polynomial-time-solvablemaximal-weighted-independent-set problem on transitive graphs. Sincedifferent supply voltages used in the circuit lead to totally differentpower consumption, we propose a fast heuristic approach to predict theoptimum dual-supply voltages by looking at the lower bound of powerconsumption in the given circuit. To deal with the possible powerpenalty due to the level converters at the interface of different supplyvoltages, we use a “constrained F-M” algorithm to minimizethe number of level converters. We have implemented our approach underan SIS environment. Experiment shows that the resulting lower bound ofpower is tight for most circuits and that the predicted“optimum” supply voltages are exactly or very close to thebest choice of actual ones. The total power saving of up to 26% (averageof about 20%) is achieved without degrading the circuit performance,compared to the average power improvement of about 7% by the gate sizingtechnique based on a standard cell library. Our technique provides thepower-delay tradeoff by specifying different timing constraints incircuits for power optimization 收起