摘要 : An improved implementation of clock synchronization of multiprocessor systems in the presence of malicious faults is proposed. The proposed hardware implementation for the reference clock selection has a lower gate complexity, sma... 展开
作者 | Choi~ B.-R. Park~ K.H. |
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期刊名称 | 《IEEE Transactions on Computers 》 |
页码/总页数 | P.404-407 / 4 |
语种/中图分类号 | 英语 / TP3 |
关键词 | Hardware Fault tolerance Clocks Frequency synchronization Multiprocessing systems Fault tolerant systems Delay effects Circuits Logic Real time systems |
DOI | 10.1109/12.48872 |
馆藏号 | IELEP0256 |