摘要 : The authors present a cell selection algorithm, ARDOR, which optimises the area of the cell-based design under the delay constraint. ARDOR visits a circuit in the forward direction and calculates the lower bound on the delay and a... 展开 The authors present a cell selection algorithm, ARDOR, which optimises the area of the cell-based design under the delay constraint. ARDOR visits a circuit in the forward direction and calculates the lower bound on the delay and area. It then binds the logic gates using the branch-and-bound formulations, while traversing the circuit in the reverse direction. Experimental results show that the ARDOR algorithm optimises the area of test circuits by 27.33% on average. 收起