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We show that the blockage in transmission of a screen with a periodic microstructure integrated over all wavelengths is bounded by the static polarizability per unit area of the screen. Physical bounds on the co-polarized transmis...
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We show that the blockage in transmission of a screen with a periodic microstructure integrated over all wavelengths is bounded by the static polarizability per unit area of the screen. Physical bounds on the co-polarized transmission coefficient over a wavelength interval are presented using only information from the zero-frequency properties of the microstructure. The theoretical results are compared to and verified by measurements on a screen composed of a large number of split ring resonators printed on a dielectric substrate. Copyright (C) EPLA, 2009
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We propose a technique for generating millimeter-wave radar waveforms using edge-triggered pulse generator circuits. By synchronizing the chip rate to the oscillation frequency of a binary control signal, a phase shift is introduc...
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We propose a technique for generating millimeter-wave radar waveforms using edge-triggered pulse generator circuits. By synchronizing the chip rate to the oscillation frequency of a binary control signal, a phase shift is introduced in the generated pulses. This way, the millimeter-wave signal can be phase-modulated without the need of additional circuit elements. We show that high-resolution radar waveforms with low range side lobes can be generated with this technique. Using brute-force optimization, we evaluate all possible sequences up to a sequence length of 25 chips and identify optimal waveforms for each length. Optimal sequences with the energy centered at zero delay and side lobes not exceeding unity are presented. The optimized waveforms are measured and verified using an in-house resonant tunneling diode (RTD) metal-oxide-semiconductor field-effect transistor (MOSFET) pulse generator. The matched filter response of the optimal waveforms is reproduced closely in the measurements. The results enable increased sensitivity in radar systems using coherent millimeter-wave pulse generators for low power applications, as for instance, radar gesture recognition in handheld devices. Using pulsed millimeter-wave radar systems with low duty cycles, continuously running oscillators can be avoided and systems with ultra-low power consumption are possible.
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Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversio...
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Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a -3 dB cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.
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We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L-g = 25 nm at a nanowire dimension of 7 x 16 nm(2). These devices use a single 7-nm-thick In0.8...
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We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L-g = 25 nm at a nanowire dimension of 7 x 16 nm(2). These devices use a single 7-nm-thick In0.80Ga0.20As (N-D = 1 x 10(19)cm(-3)) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g(m) = 1.6 mS/mu m and I-ON = 160 mu A/mu m (at I-OFF = 100 nA/mu m and V-DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer. (c) 2017 The Japan Society of Applied Physics
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We analyze the downlink of a massive multiuser multiple input, multiple output (MIMO) system where antenna units at the base station are connected in a daisy chain without a central processing unit and only possess local channel k...
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We analyze the downlink of a massive multiuser multiple input, multiple output (MIMO) system where antenna units at the base station are connected in a daisy chain without a central processing unit and only possess local channel knowledge. For this setup, we develop and analyze a linear precoding algorithm for suppressing interuser interference. It is demonstrated that the algorithm is close to zero-forcing precoding in terms of performance for a large number of antennas. Moreover, we show that with careful scheduling of processing across antennas, requirements for interconnection throughput are reduced compared with the fully centralized solution. Favorable tradeoff between performance and interconnection throughput makes the daisy chain a viable candidate topology for real-life implementations of base stations in MIMO systems where the number of antennas is very large.
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Local pseudorandom generators are a class of fundamental cryptographic primitives having very broad applications in theoretical cryptography. Following Couteau et al.'s work at ASIACRYPT 2018, this paper further studies the concre...
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Local pseudorandom generators are a class of fundamental cryptographic primitives having very broad applications in theoretical cryptography. Following Couteau et al.'s work at ASIACRYPT 2018, this paper further studies the concrete security of one important class of local pseudorandom generators, i.e., Goldreich's pseudorandom generators. Our first attack is of the guess-and-determine type. Our result significantly improves the state-of-the- art algorithm proposed by Couteau et al., in terms of both asymptotic and concrete complexity, and breaks all the challenge parameters they proposed. For instance, for a parameter set suggested for 128 bits of security, we could solve the instance faster by a factor of about 2(77), thereby destroying the claimed security completely. Our second attack further exploits the extremely sparse structure of the predicate P-5 and combines ideas from iterative decoding. This novel attack, named guess-and-decode, substantially improves the guess-and-determine approaches for cryptographic-relevant parameters. All the challenge parameter sets proposed in Couteau et al.'s work in ASIACRYPT 2018 aiming for 80-bit (128-bit) security levels can be solved in about 2(58) (2(78)) operations. We suggest new parameters for achieving 80-bit (128-bit) security with respect to our attacks. We also extend the attacks to other promising predicates and investigate their resistance.
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To enable realistic studies of massive multiple-input multiple-output systems, the COST 2100 channel model is extended based on measurements. First, the concept of a base station-side visibility region (BS-VR) is proposed to model...
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To enable realistic studies of massive multiple-input multiple-output systems, the COST 2100 channel model is extended based on measurements. First, the concept of a base station-side visibility region (BS-VR) is proposed to model the appearance and disappearance of clusters when using a physically-large array. We find that BS-VR lifetimes are exponentially distributed, and that the number of BS-VRs is Poisson distributed with mean proportional to the sum of the array length and the mean lifetime. Simulations suggest that under certain conditions longer lifetimes can help decorrelating closely-located users. Second, the concept of a multipath component visibility region (MPC-VR) is proposed to model birth-death processes of individual MPCs at the mobile station side. We find that both MPC lifetimes and MPC-VR radii are lognormally distributed. Simulations suggest that unless MPC-VRs are applied the channel condition number is overestimated. Key statistical properties of the proposed extensions, e.g., autocorrelation functions, maximum likelihood estimators, and Cramer-Rao bounds, are derived and analyzed.
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We present a new algorithm for solving the LPN problem. The algorithm has a similar form as some previous methods, but includes a new key step that makes use of approximations of random words to a nearest codeword in a linear code...
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We present a new algorithm for solving the LPN problem. The algorithm has a similar form as some previous methods, but includes a new key step that makes use of approximations of random words to a nearest codeword in a linear code. It outperforms previous methods for many parameter choices. In particular, we can now solve the LPN instance with complexity less than operations in expectation, indicating that cryptographic schemes like HB variants and LPN-C should increase their parameter size for 80-bit security.
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In-memory computing can be used to overcome the von Neumann bottleneck-the need to shuffle data between separate memory and computational units-and help improve computing performance. Co-integrated vertical transistor selectors (1...
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In-memory computing can be used to overcome the von Neumann bottleneck-the need to shuffle data between separate memory and computational units-and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III-V semiconductor nanowire and a high-kappa dielectric (hafnium oxide), which provides an oxide layer that can operate either as a vertical transistor selector or a high-performance resistive memory. The resulting 1T1R cells allow Boolean logic operations to be implemented in a single vertical nanowire with a minimal area footprint.A vertical transistor and resistive memory can be integrated on a single vertical III-V semiconductor nanowire on silicon, creating a compact cell capable of Boolean logic operations.
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In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping le...
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In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices. The best devices reached a point subthreshold swing of 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. An increase in the doping level helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation with the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs.
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