摘要 :
The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D integrated circuits (ICs). Different modeling strategies have been implemented to this scope,...
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The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D integrated circuits (ICs). Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multiscale strategy, whose core is constituted by a highly resolved, convolution-based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time-dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite-element method results shows good accuracy. An error metric, to estimate the need to include the package impact on top of the convolution-based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this paper.
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It will be shown in this contribution that if the thermal impedance Zth(jw)of an electronic package is represented in a Nyquist plot, the curve obtained can be fitted very well to a combination of a few (n) circles, n varying betw...
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It will be shown in this contribution that if the thermal impedance Zth(jw)of an electronic package is represented in a Nyquist plot, the curve obtained can be fitted very well to a combination of a few (n) circles, n varying between 2 and a maximum of 5. For each of these circles, it is sufficient to know the radius and the coordinates of the center point or just three parameters. With 3n parameters the entire behavior of the impedance can be represented and consequently, the dynamic behavior as well.
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This article is focused on the thermal design and three-dimensional (3-D) package optimization of planar magnetic components (PMCs), including transformers and inductors for application in an electric vehicle composite boost dc–d...
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This article is focused on the thermal design and three-dimensional (3-D) package optimization of planar magnetic components (PMCs), including transformers and inductors for application in an electric vehicle composite boost dc–dc converter. Each PMC comprises electrical windings in printed circuit board (PCB) form in combination with a ferrite core. Multiple features of each PMC package are thermally optimized for the proposed device configurations with given core size, core loss distribution, number of turns in the PCB winding, winding copper thickness, and winding loss distribution. These heuristically optimized features include a lower level cold plate structure with a conformal base for enhanced convective heat transfer, an upper level PMC cap structure for doubled-sided cooling through conductive heat flow to the cold plate, the implementation of functionally distributed copper thermal and electrothermal vias in the PCB winding for improved cross-plane thermal conductance, and judicious implementation of select materials at various locations and interfaces within the package. Detailed numerical modeling reveals the combined effect of this 3-D packaging strategy with a 79.3 °C and 48.5 °C maximum temperature reduction in the core and PCB winding, respectively, relative to a baseline device configuration. Select PMC experimental validation confirms the expected thermal performance of an optimized PCB design. The thermal design approach is relevant for a range of high-power-density electronics PMC packaging applications.
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The thermal contact resistance caused by the rough contact interface accounts for a large proportion of the total thermal resistance of microelectronic devices. In this article, the influencing factors of the contact thermal resis...
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The thermal contact resistance caused by the rough contact interface accounts for a large proportion of the total thermal resistance of microelectronic devices. In this article, the influencing factors of the contact thermal resistance between copper-indium interface in electronic packaging has been investigated using numerical calculation methods. The Weierstrass-Mandelbrot fractal function was used to establish the copper-indium contact surface morphology with different surface characteristics. The temperature field of the copper-indium contact model with different surface roughness was calculated by the finite element method, and the influence of pressure on the contact thermal resistance was analyzed. The heat transfer behavior of the interface gap medium was simulated by setting the thermal contact conductivity that changed with the contact gap distance. The influence of air and grease in the thermal resistance of copper-indium contact was investigated. It was indicated that 1) pressure will rapidly reduce the contact thermal resistance, but the cost-effectiveness ratio gradually decreases and 2) influence of air on the contact thermal resistance decreases rapidly as the pressure increases, but grease has a significant effect under various pressure conditions.
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The author contends that packaging and interconnection technology is undergoing significant changes to meet the rapidly evolving requirements of portable electronics products. The need for high density and high performance at low ...
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The author contends that packaging and interconnection technology is undergoing significant changes to meet the rapidly evolving requirements of portable electronics products. The need for high density and high performance at low cost demands sophisticated developments in technology. Future portable equipment packaging requirements can be met only through advanced concepts, including multichip modules, tape-automated bonding, and flip-chip assembly. Supporting technologies, such as adhesive assembly, thermal management, and design tools must also make attendant advances. Consortium-based cooperative research and development of technologies addresses these needs, while also developing the essential vendor infrastructure.
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This paper presents a thermal architecture concept for analysis of thermal problems and solutions existing in electronics systems. The thermal problems are categorized into a total of seven levels from chip to system. Advanced the...
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This paper presents a thermal architecture concept for analysis of thermal problems and solutions existing in electronics systems. The thermal problems are categorized into a total of seven levels from chip to system. Advanced thermal technologies for addressing the thermal problems at all seven levels are discussed. Integrating the thermal architecture with the electronic architecture can significantly improve the effectiveness of the thermal management.
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Compact thermal models have been constructed for different levels in electronic systems with a variable degree of success. In this work first steps toward constructing a unifying theory are presented for linear systems giving gene...
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Compact thermal models have been constructed for different levels in electronic systems with a variable degree of success. In this work first steps toward constructing a unifying theory are presented for linear systems giving general constraints on the form of the compact model that will ensure an adequate description of thermal systems. The theory is also used to study the completeness of the set of boundary conditions used to derive and/or validate thermal compact models.
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Thermal management plays a very vital role in the packaging of high performance electronic devices. Effective heat dissipation is crucial to enhance the performance and reliability of the packaged devices. Liquid encapsulants used...
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Thermal management plays a very vital role in the packaging of high performance electronic devices. Effective heat dissipation is crucial to enhance the performance and reliability of the packaged devices. Liquid encapsulants used for glob top, potting, and underfilling applications can strongly influence the package heat dissipation. Unlike molding compounds, the filler loading in these encapsulants is restrained. This paper deals with the development and characterization of thermally conductive encapsulants with relatively low filler loading. A comparative study on the effect of different ceramic fillers on the thermal conductivity and other critical properties of an epoxy based liquid encapsulant is presented
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DRAM is usually used as main memory for program execution. The thermal behavior of a memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a ...
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DRAM is usually used as main memory for program execution. The thermal behavior of a memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system, while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware memory allocator should consider the following two points. First, the allocator should consider not only the power behavior of a logic block but also the physical location during memory mapping and second, the changing temperature of a physical block during execution of programs. In this article, we will propose a memory mapping algorithm taking into consideration these two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that for single-core systems, our method can reduce the temperature of memory system by 17.1℃, as compared to a straightforward mapping in the best case, and 13.3℃ on average. For systems with four cores, the temperature reductions are 9.9℃ and 11.6℃ on average when L1 cache of each core is set to 4KB and 8KB, respectively.
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We explore a modified thermal resistance analysis by induced transient method applied to light emitting diodes (LEDs) to discretize the junction-to-package thermal resistance. The temperature response of LED and package configurat...
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We explore a modified thermal resistance analysis by induced transient method applied to light emitting diodes (LEDs) to discretize the junction-to-package thermal resistance. The temperature response of LED and package configuration is evaluated for discrete contributions from identifiable spatial domains in the multilayered device and package structure to obtain their thermal resistances and thermal capacitances using a Laplace transform-based method. The technique successfully extracts the junction-to-package thermal parameters of a variety of LED package configurations from the experimental temperature transient measurements of the LED junction and provides a straightforward method by which these parameters can be obtained.
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