摘要 :
The method of electrical inversion in classical electrostatics is employed to obtain exact solutions for basic electrostatic problems pertaining to overlapping spheres/cylinders. The problems considered here include (1) a pair of ...
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The method of electrical inversion in classical electrostatics is employed to obtain exact solutions for basic electrostatic problems pertaining to overlapping spheres/cylinders. The problems considered here include (1) a pair of overlapping conducting spheres, intersecting at a vertex angle π/n, n an integer, placed in a constant potential field; (2) a pair of infinitely long conducting circular cylinders, intersecting at a vertex angle π/n, n an integer, placed in a uniform field; and (3) a composite hybrid geometry consisting of two orthogonally intersecting infinitely long circular cylinders whose boundary is a combination of conducting and dielectric surfaces (with mixed boundary conditions) submerged in a uniform field. Applying the basic idea of Kelvin's inversion repeatedly, solutions for the electric potentials are derived in each case. An exact expression for the capacitance in terms of the two radii, center-to-center distance, and the vertex angle is found for the twin sphere geometry. The capacity is then used to find the steady-state rate coefficient of a perfectly absorbing body placed in a thermally conducting environment of lower temperature. The equipotentials are plotted using the exact solutions of the two-dimensional problems and their features are discussed as well. The simple method illustrated here can be useful both as a teaching tool and as a building block for further computations.
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摘要 :
The method of electrical inversion in classical electrostatics is employed to obtain exact solutions for basic electrostatic problems pertaining to overlapping spheres/cylinders. The problems considered here include (1) a pair of ...
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The method of electrical inversion in classical electrostatics is employed to obtain exact solutions for basic electrostatic problems pertaining to overlapping spheres/cylinders. The problems considered here include (1) a pair of overlapping conducting spheres, intersecting at a vertex angle π/n, n an integer, placed in a constant potential field; (2) a pair of infinitely long conducting circular cylinders, intersecting at a vertex angle π/n, n an integer, placed in a uniform field; and (3) a composite hybrid geometry consisting of two orthogonally intersecting infinitely long circular cylinders whose boundary is a combination of conducting and dielectric surfaces (with mixed boundary conditions) submerged in a uniform field. Applying the basic idea of Kelvin’s inversion repeatedly, solutions for the electric potentials are derived in each case. An exact expression for the capacitance in terms of the two radii, center-to-center distance, and the vertex angle is found for the twin sphere geometry. The capacity is then used to find the steady-state rate coefficient of a perfectly absorbing body placed in a thermally conducting environment of lower temperature. The equipotentials are plotted using the exact solutions of the two-dimensional problems and their features are discussed as well. The simple method illustrated here can be useful both as a teaching tool and as a building block for further computations.
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Analytical expressions for the gate-voltage dependence of the channel capacitance and the gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs) are derived and implemented in an organic compact...
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Analytical expressions for the gate-voltage dependence of the channel capacitance and the gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs) are derived and implemented in an organic compact capacitance model. The resulting modified model is verified by experimental data of transistors with constant mobility. The same model is analyzed by numerical simulations for OTFTs with a voltage-dependent mobility. The simulation results indicate that the quasistatic model describes well the simulated capacitances. In accumulation, the modeled values are slightly overestimated because of the generally accepted assumption of the charge-sheet model. It is also demonstrated that the quasistatic regime occurs at lower frequencies because of the reduced mobility at lower charge carrier concentrations.
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Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction o...
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Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_(ov) and fringing C_(if) + C_(of) capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.
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In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-paramete...
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In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-parameters. The accuracy of extraction method is verified by observing good agreements between the measured and modeled S-parameters. The lateral channel doping profile in the drain region is experimentally measured using a Vds-dependent curve of the overlap and depletion length obtained from the extracted data.
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Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (N...
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Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f_T) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.
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The design, fabrication, and mechanical characterization of a compact-reduced stiction see-saw radio frequency MEMS switch are presented. The switch has a resonance frequency of 9.8 kHz with a corresponding switching speed of 46 μ...
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The design, fabrication, and mechanical characterization of a compact-reduced stiction see-saw radio frequency MEMS switch are presented. The switch has a resonance frequency of 9.8 kHz with a corresponding switching speed of 46 μs. Use of a floating metal layer and optimal contact area ensures reduced stiction and smaller capacitive leakage. Overall size of the switch is 0.535 (0.50 × 1.070) mm~2. Reduction in up-state capacitance also results in improvement in self-actuation voltage, insertion, and return loss. The optimized topology has improved the stiction and power handling of the switch.
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We report an experimental characterization of the interface states (D-it(E)) by using the subthreshold drain current with optical charge pumping effect in In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs)...
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We report an experimental characterization of the interface states (D-it(E)) by using the subthreshold drain current with optical charge pumping effect in In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The interface states are derived from the difference between the dark and photo states of the current-voltage characteristics. We used a sub-bandgap photon (i.e., with the photon energy lower than the bandgap energy, E-ph < E-g) to optically excite trapped carriers over the bandgap in In0.53Ga0.47As MOSFETs. We combined a gate bias-dependent capacitance model to determine the channel length-independent oxide capacitance. Then, we estimated the channel length-independent interface states in In0.53Ga0.47As MOSFETs having different channel lengths (L-ch = 5, 10, and 25 [mu m]) for a fixed overlap length (L-ov = 5 [mu m]).
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In modern satellite communication systems and airborne repeaters using an APAR, the receiving and transmitting modules usually consist of discrete phase shifters such as hybrid integrated circuits or monolithic circuits. In this p...
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In modern satellite communication systems and airborne repeaters using an APAR, the receiving and transmitting modules usually consist of discrete phase shifters such as hybrid integrated circuits or monolithic circuits. In this paper, we consider an open-frame analog-digital phase shifter module with a 0°-360° phase change that allows ensuring the accuracy of setting the discrete phase to not more than 0.5° based on the domestic control UHF MIS varicaps. An original L-range analog-digital phase shifter with a 0°-360° phase change using a Lange bridge and phase-shifting cells based on four UHF MIS varicaps is proposed. The requirements for the type of volt-farad characteristic and the capacitance overlap coefficient of the MDP-varicap capacitance are determined. Even at the limiting (critical) UHF MIS-varicap frequency not higher than 15 GHz, the proposed scheme of the analog-digital phase shifter allows ensuring the phase shifter loss that is not greater than 1.5 dB in the L-band. The analog-digital phase shifter with a 0°-360° phase change was operated by the digital control board. An 8-bit DAC was used. The division value of the discrete control of the phase shifter is 1.4° at 256 DAC states. The obtained characteristics of the precision analogdigital phase shifter allow concluding on the propects of its use for solving synchronization problems of an active radio target simulator in testing synthetic aperture radars, as well as in the receiving and transmitting modules of a low-element APAR for the L-band.
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Low-parasitic-capacitance 4H-SiC pMOSFETs using pseudo-self-aligned process were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain c...
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Low-parasitic-capacitance 4H-SiC pMOSFETs using pseudo-self-aligned process were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.
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