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Self-patterning of thin films using photosensitive sol-gel solution has advantages such as simple manufacturing process compared to photoresist/dry etching process. In this study, ferroelectric Sr0.9Bi2.1Ta2O9 thin films have been...
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Self-patterning of thin films using photosensitive sol-gel solution has advantages such as simple manufacturing process compared to photoresist/dry etching process. In this study, ferroelectric Sr0.9Bi2.1Ta2O9 thin films have been prepared by spin coating method using photosensitive sol-gel solution. Strontium ethoxide, tetramethylheptanedionato bismuth and tantalum ethoxide were used as starting materials. As UV exposure time to the SBT thin film increases, the intensity of UV absorption peak of metal beta-diketonate decreases due to degradation of solubility resulted from Metal-Oxygen-Metal (M-O-M) bond formation. The solubility difference by UV irradiation on SBT thin film allows to obtain a fine patterning of thin film. The ferroelectric properties of the UV irradiated SBT thin films are superior to those of the non-UV irradiated film. (C) 2003 Kluwer Academic Publishers. [References: 7]
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Emerging nonvolatile memories (NVMs) suffer from low write endurance, resulting in early cell failures (hard errors), which reduce memory lifetime. It was recognized early on that conventional error-correcting codes (ECCs), which ...
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Emerging nonvolatile memories (NVMs) suffer from low write endurance, resulting in early cell failures (hard errors), which reduce memory lifetime. It was recognized early on that conventional error-correcting codes (ECCs), which are designed for soft errors, are a poor choice for addressing hard errors in NVMs. This led to the evolution of hard error correction schemes like dynamically replicated memory (DRM), error-correcting pointers (ECPs), SAFER, FREE-p, PAYG, and Zombie memory to improve NVM lifetime. Whereas these approaches made significant inroads in addressing hard errors and low memory lifetime in NVMs, overcoming the challenges of underutilization of error-correcting resources and/or implementation overhead (e.g., codec latency, hardware support) remain areas of active research and development.
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A generalized rewriting model is defined for flash memory that represents stored data and permitted rewrite operations by a directed graph. This model is a generalization of previously introduced rewriting models of codes, includi...
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A generalized rewriting model is defined for flash memory that represents stored data and permitted rewrite operations by a directed graph. This model is a generalization of previously introduced rewriting models of codes, including floating codes, write-once memory codes, and buffer codes. This model is used to design a new rewriting code for flash memories. The new code, referred to as trajectory code, allows stored data to be rewritten as many times as possible without block erasures. It is proved that the trajectory codes are asymptotically optimal for a wide range of scenarios. In addition, rewriting codes that use a randomized rewriting scheme are presented that obtain good performance with high probability for all possible rewrite sequences.
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In this paper, the NiSi_2/SiN_x compound NCs (CNCs) structure is studied to further improve the retention. To introduce the nitride based traps, NiSi2 was also sputtered in the mixture gas of Ar (50 sccm) and NH_3 (10 sccm) at roo...
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In this paper, the NiSi_2/SiN_x compound NCs (CNCs) structure is studied to further improve the retention. To introduce the nitride based traps, NiSi2 was also sputtered in the mixture gas of Ar (50 sccm) and NH_3 (10 sccm) at room temperature, and the NiSi_2/SiN_x CNCs can be easily formed after rapid thermal annealing. In addition, standard memory devices with single and double NiSi_2 nanocrystal were also prepared for comparison. By XPS analyses, the nanocrystals fabricated in the ambiance of NH_3 can be confirmed to be composited of NiSi_2 and SiN_x compound. According to memory characteristics results, better retention characteristic of device with single-layer NiSi_2/SiN_x compound nanocrystal NVMs can be observed after 10~4 s, raises from 50% to 72% in comparison with the control sample, even better than the double-layer NiSi_2 nanocrystal, 58%. Indeed, the formation of NiSi_2/SiN_x CNCs can improve the retention characteristics remarkably due to the additional tunnel barrier and deep traps in the nitride.
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A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high- speed nonvolatile memory. One memory cell consists of one tran- sistor and one ferroelectric capacitor connected in parallel,...
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A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high- speed nonvolatile memory. One memory cell consists of one tran- sistor and one ferroelectric capacitor connected in parallel, and one memory one ferroelectric capacitor connected in parallel, and ing transistor in series. This configuration realizes small memory cell of 4F~2 size and fast random access time.
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We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr_(0.35),Ti_(0.65))O_3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor d...
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We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr_(0.35),Ti_(0.65))O_3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol-gel methods, respectively. Such PZT films show a high remnant polarization (P_r) of 30 μ_C cm ~(-2) and a coercive voltage (V_c) of 3.5 V under a voltage loop over ±11 V. The graphene-PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.
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Effects of imprint on signal margin in FeRAM with Pt/SrBi_2Ta_2O_9/Pt capacitors have been investigated. Im- print, induced during high temperature storage, significantly re- duced the signal margin and hence determines lifetime o...
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Effects of imprint on signal margin in FeRAM with Pt/SrBi_2Ta_2O_9/Pt capacitors have been investigated. Im- print, induced during high temperature storage, significantly re- duced the signal margin and hence determines lifetime of FeRAM. Initial signal margin of 470mV is reduced to 290mV after storage At 175℃for 96 hours. From the reduction rate of the signal mar- gin, it is estimated that imprint lifetime of the FeRAM is more than 10 years even though the storage temperature is 175℃.
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New ferroelectric Pb(Zr,Ti)O-3-Pb(Mn,WSb,Nb)O-3 (PZT-PMWSN) thin film has been deposited on a Pt/Ti/SiO2/Si substrate by pulsed laser deposition. Buffer layer was adopted between film and substrate to improve the ferroelectric pro...
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New ferroelectric Pb(Zr,Ti)O-3-Pb(Mn,WSb,Nb)O-3 (PZT-PMWSN) thin film has been deposited on a Pt/Ti/SiO2/Si substrate by pulsed laser deposition. Buffer layer was adopted between film and substrate to improve the ferroelectric properties of PZT-PMWSN films. Effect of a Pb(Zr0.52Ti0.48)O-3 (PZT) and (Pb0.72La0.28)Ti0.93O3 (PLT) buffer layers on the stabilization of perovskite phase and the suppression of pyrochlore phase has been examined. Role of buffer layers was investigated depending on different types of buffer layer and thickness. The PZT-PMWSN thin films with buffer layer have higher remnant polarization and switching polarization values by suppressing pyrochlore phase formation. The remnant polarization, saturation polarization, coercive field and relative dielectric constant of 10-nm-thick PLT buffered PZT-PMWSN thin film with no pyrochlore phase were observed to be about 18.523 mu C/cm(2), 47.538 mu C/cm(2). 63.901 kV/cm and 854, respectively. (c) 2005 Elsevier B.V. All rights reserved.
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With the wide application of NAND flash storage systems in read-intensive memory, the corresponding reliability enhancement strategies for mitigating read disturb become the focus of investigations in recent years. The prior inves...
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With the wide application of NAND flash storage systems in read-intensive memory, the corresponding reliability enhancement strategies for mitigating read disturb become the focus of investigations in recent years. The prior investigations have reported the strategies based on data modulation and verified their effectiveness in mitigating retention loss. The most significant advantage of these strategies is that they can often achieve significant reliability enhancement effect with great read performance, since they are usually based on asymmetric coding. This feature means that they have the potential to be ideal reliability enhancement strategies for read-intensive memory applications. To propose a universal and highly reliable data storage strategy, this article first observes the error modes at the cell-state level under the reliability stresses of retention loss and read disturb with floating-gate (FG) 3-D triple-level (TLC) NAND flash, and then proposes a target cell states elimination (TCSE) coding strategy for further restraining bit errors. In addition, this article for the first time reports the extra bit errors generated in the decoding process of the storage strategies based on data modulation, and defines the concept of transfer factor (TF) for evaluation. By using the proposed TCSE, the experimental results show that the overall bit error rate (BER) can be reduced by 80%–90% on average, compared with the raw random data pattern.
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Multi-level memory cells are used in non-volatile memories to increase the storage density. Using multi-level cells, however, imposes lower read and write speeds, limiting their usability with high-performing applications. In this...
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Multi-level memory cells are used in non-volatile memories to increase the storage density. Using multi-level cells, however, imposes lower read and write speeds, limiting their usability with high-performing applications. In this work we study the tradeoff between storage density and write/read speeds using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give a detailed analytical treatment of their information rate and speed, provide encoding/decoding algorithms, and compare them with more basic access schemes and upper bounds. Using performance coding enables accessing the memory with variable access speeds, thus creating heterogenous storage devices serving a variety of applications with improved efficiency.
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