摘要 :
In mixed-signal integrated circuits (IC's), substrate noise produced by high-speed digital circuits passes to the on-chip analog circuits through the substrate and seriously degrades their performance. We have developed a method f...
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In mixed-signal integrated circuits (IC's), substrate noise produced by high-speed digital circuits passes to the on-chip analog circuits through the substrate and seriously degrades their performance. We have developed a method for measuring the substrate noise by using noise-selective chopper-type voltage comparators as noise detectors. This method can detect the wide-band substrate noise so we can analyze and further reduce its effect. A switched capacitance is selectively loaded on the output of the inverter amplifier of the comparator during the comparison period in order to reduce the noise detected at the transition from compare to auto-zero. In contrast, the noise at the transition from auto-zero to compare can be selectively detected. Waveforms of high-frequency substrate noise were reconstructed by using this on-chip-noise detector incorporating the noise-selective comparators implemented using a 0.5-/spl mu/m CMOS bulk process.
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This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effec...
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This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.
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In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts ...
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In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.
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In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, ...
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In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.
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In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power non-critical paths and high-speed critical paths...
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In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power non-critical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual time-consuming approach based on iterative simulations with a trial-and-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.
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A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc...
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A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.
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The digital image transmission IC digitizes and compresses picture signals from a camera for transmission over a twisted paired cable, allowing easy and inexpensive application in household video monitoring systems. Three types of...
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The digital image transmission IC digitizes and compresses picture signals from a camera for transmission over a twisted paired cable, allowing easy and inexpensive application in household video monitoring systems. Three types of integrated circuits have been developed. An encoder IC which subjects the digitized video signals to data compression and sends and receives control signals; a decoder IC that receives video data from the encoder IC and outputs composite analog video signals; and a hybrid IC which integrates an encoder IC with the majority of its peripheral circuits (including A/D conversion circuits and memory). The main specifications of the three ICs are indicated.
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The changing face of circuit design is described in this paper. With the invention of the integrated circuit (IC) and the development and continual improvement of the metal-oxide-semiconductor field-effect transistor (MOSFET), hav...
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The changing face of circuit design is described in this paper. With the invention of the integrated circuit (IC) and the development and continual improvement of the metal-oxide-semiconductor field-effect transistor (MOSFET), have brought tremendous changes to the circuit design area. The three types of circuits commonly fabricated on a chip are analog, digital, and mixed signal. Although the IC has led to tremendous developments in the electronics field, the process of IC circuit design has become more difficult. The large range and accuracy of component values in discrete design make the design less difficult. Special methods that apply active loads and matching techniques are required in IC design to minimize the number of resistors used and to remove the dependence of circuit performance on element values. Perhaps the most difficult part of IC design is the time lag between design and fabrication of the circuit, which may be several weeks or even months. Discrete circuits are often constructed within hours of completion of the initial paper design
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The authors have reduced the size of multichannel analyzers (MCAs) and have implemented more features in hardware to relieve software requirements. They built and tested a spectroscopy grade, 4096-channel MCA. Most of the hardware...
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The authors have reduced the size of multichannel analyzers (MCAs) and have implemented more features in hardware to relieve software requirements. They built and tested a spectroscopy grade, 4096-channel MCA. Most of the hardware logic was implemented using a programmable, application-specific digital integrated circuit (ASIC). The ASIC not only reduced the size of the circuitry, but resulted in great versatility without relayout of the circuit boards. These ASIC techniques were used in a design to enhance the high-count-rate throughput of the portable MCA used extensively in safeguards. Exclusive of amplifier and power supply, the MCA fits on two boards each approximately 7 by 15 cm. The features and performance of the analyzer and some reasonable applications of these technologies are discussed.
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摘要 :
More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, infor...
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More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.
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