摘要: In this paper, we present the modeling and implementation of a FPGA-based Digital Band-Pass FIR (DBPF) filter to reduce the undesired noise levels in raw ultrasound data. The cascaded tapped delay line FIR filter was built within ... 展开 In this paper, we present the modeling and implementation of a FPGA-based Digital Band-Pass FIR (DBPF) filter to reduce the undesired noise levels in raw ultrasound data. The cascaded tapped delay line FIR filter was built within the Simulink environment combined with the DSP Builder toolbox, allowing easy and automatic generation of synthesizable VHDL code. In order to demonstrate the feasibility and flexibility of our design, we employed eight symmetrical 8-tap cascaded FIR filter structures to implement a 64-tap DBPF filter. The fractional coefficient values were obtained by the equiripple design method assuming a pass-band frequency between 1.4 and 5 MHz, stop-band of -50 dB and sampling frequency of 40 MHz. The experimental implementation was done on an Intel Stratix IV FPGA by using a linear chirp signal and real raw data added with DC and low- and high-noise frequency components. The accuracy of the model was analyzed by using the normalized root mean square error (NRMSE) cost function for comparison with a reference filter structure designed with FDATool and exported to Simulink. An excellent agreement was achieved between the simulation and experimental results. The overall FPGA utilization was less than 5% and the calculated NRMSE was 0.013%, corroborating the effectiveness of the proposed hardware architecture. 收起