摘要: A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor ra... 展开
作者 | Chidambaram, Sundaresan Chaitanya, Vishnu Satya | ||
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文集名称 | 2013 4th International conference on intelligent systems, modelling and simulation | ||
出版年 | 2013 | ||
出版社/出版地 | Institute of Electrical and Electronics Engineers / Piscataway | ||
会议名称 | International Conference on Intelligent Systems, Modelling and Simulation | ||
开始页/总页数 | 592 / 4 | ||
会议日期/会议地点 | 20130129-31 / Bangkok | 会议年/会议届次 | 2013 / 4th |
中图分类号 | TP18-53 | ||
关键词 | clock clock division clock multiplication | ||
馆藏号 | N2013EMST0002343 |