摘要: On-chip memory dominates die area for most processor and logic designs. For the last several years embedded DRAM has become successful in replacing conventional SRAM for many of these applications. We will outline the key requirem... 展开 On-chip memory dominates die area for most processor and logic designs. For the last several years embedded DRAM has become successful in replacing conventional SRAM for many of these applications. We will outline the key requirements of embedded memory and the tradeoffs between SRAM and DRAM for these applications. As scaling has progressed into the 45 nm regime and beyond, SRAM scaling has become more difficult and it has become difficult to reduce the SRAM voltages due to instabilities that develop as voltage is lowered. Embedded DRAMs offer a 3-4X density advantage, a better than 5X standby power advantage, and a significantly higher resistance to soft error upsets. In the future, three dimensional integration (3Di) of circuits is an attractive approach to stay on the semiconductor productivity roadmap. Briefly, the principal value of 3-D integration lies in increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. However, as we study this problem in some detail we uncover a serious set of constraints especially for high performance applications. These constraints can be classified in four broad categories: the overhead and design constraints of through silicon vias (TSVs); Power delivery and distribution in multiple strata; heat dissipation across the 3 D stack; and finally reparability of the 3D stack. In this talk we will examine these constraints in detail based on our experience with high end processors. 收起