摘要 : This paper presents a low nonlinearity, four channel Gated Ring Oscillator (GRO) based Time-to-Digital Converters (TDC) in Xilinx 28 nm Virtex 7 Field Programmable Gate Arrays. Gray code counter provides a coarse time measurement ... 展开 This paper presents a low nonlinearity, four channel Gated Ring Oscillator (GRO) based Time-to-Digital Converters (TDC) in Xilinx 28 nm Virtex 7 Field Programmable Gate Arrays. Gray code counter provides a coarse time measurement value, and the fine residue information is obtained from the 64 stages of sampling registers outputs. GRO based TDC places the carry logics as a delay element in a ring topology such that it can be reused for measuring large time intervals. Online calibration by the code density analysis is implemented to minimize linearity errors. After calibration and normalization, the proposed architecture has achieved an improved Differential Non-linearity in the range of [- 0.12, 0.11] LSB, and Integral Non-linearity in the range of [- 0.2, 0.4] LSB. The proposed architecture is also cost effective in terms of resource consumption with a high resolution of 15 ps. 收起