摘要: Memory-CPU single communication channel bottleneck of the von Neumann architecture is quickly stalling the growth of computer processors. A probable solution to this problem is to fuse processing and memory elements. A simple low ... 展开
作者 | Mohammed Ziaur Rahman | ||
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作者单位 | |||
文集名称 | Algorithms and architectures for parallel processing | ||
出版年 | 2011 | ||
会议名称 | ICA3PP 2011;International conference on algorithms and architectures for parallel processing | ||
卷/页码 | part 1 / p.306-317 | 开始页/总页数 | 00000306 / 12 |
会议日期/会议地点 | 20111024-26;20111024-26 / Melbourne(AU);Melbourne(AU) | 会议年/会议届次 | 2011 / 11th;11th |
中图分类号 | TP39 | ||
关键词 | computer architectures parallel architectures memory architectures | ||
馆藏号 | P1102675 |