摘要: This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length ... 展开
作者 | Zhipeng Liu Jinian Bian Qiang Zhou Hui Dai | ||
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出版年 | 2007 | ||
页码 | 279-284 | 开始页/总页数 | 00000279 / 6 |
关键词 | delays integrated circuit design integrated circuit interconnections integrated circuit layout floorplanning integrated circuit design interconnect delay interconnect wire length module duplication power optimization | ||
馆藏号 | IEEE-IEL |