摘要 : A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 interpolation factor with only dynamic comparators. A background latching-time adjustment sc... 展开 A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 interpolation factor with only dynamic comparators. A background latching-time adjustment scheme utilizing a replica latch array ensures an interpolation capability that is robust to process, voltage and temperature variations. The measured peak INL and DNL of 0.64 LSB and 0.58 LSB, respectively, after comparator offset calibration prove successful interpolation operation. The measured SNDR and SFDR were 38.12 dB and 49.05 dB, respectively, with a 1.08GHz input at 2 GS/s operation while consuming 20.7 mW of total power. This ADC achieves a figure of merit of 157 fJ/conversion-step with a Nyquist input at 2 GS/s. 收起