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The Goppa Code Distinguishing (GD) problem consists in distinguishing the matrix of a Goppa code from a random matrix. The hardness of this problem is an assumption to prove the security of code-based cryptographic primitives such...
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The Goppa Code Distinguishing (GD) problem consists in distinguishing the matrix of a Goppa code from a random matrix. The hardness of this problem is an assumption to prove the security of code-based cryptographic primitives such as McEliece's cryptosystem. Up to now, it is widely believed that the GD problem is a hard decision problem. We present the first method allowing to distinguish alternant and Goppa codes over any field. Our technique can solve the GD problem in polynomial time provided that the codes have sufficiently large rates. The key ingredient is an algebraic characterization of the key-recovery problem. The idea is to consider the rank of a linear system which is obtained by linearizing a particular polynomial system describing a key-recovery attack. It appears that this dimension depends on the type of code considered. Explicit formulas derived from extensive experimentations for the rank are provided for “generic” random, alternant, and Goppa codes over any field. Finally, we give theoretical explanations of these formulas in the case of random codes, alternant codes over any field of characteristic two and binary Goppa codes.
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This paper presents a quantum-based algorithm for evolving artificial neural networks (ANNs). The aim is to design an ANN with few connections and high classification performance by simultaneously optimizing the network structure ...
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This paper presents a quantum-based algorithm for evolving artificial neural networks (ANNs). The aim is to design an ANN with few connections and high classification performance by simultaneously optimizing the network structure and the connection weights. Unlike most previous studies, the proposed algorithm uses quantum bit representation to codify the network. As a result, the connectivity bits do not indicate the actual links but the probability of the existence of the connections, thus alleviating mapping problems and reducing the risk of throwing away a potential candidate. In addition, in the proposed model, each weight space is decomposed into subspaces in terms of quantum bits. Thus, the algorithm performs a region by region exploration, and evolves gradually to find promising subspaces for further exploitation. This is helpful to provide a set of appropriate weights when evolving the network structure and to alleviate the noisy fitness evaluation problem. The proposed model is tested on four benchmark problems, namely breast cancer and iris, heart, and diabetes problems. The experimental results show that the proposed algorithm can produce compact ANN structures with good generalization ability compared to other algorithms.
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A 2.4-GHz industrial scientific and medical band binary frequency-shift-keying transmitter embedded in the Hypothesis, Odyssey, and Yield (HOY) wireless test system is presented and implemented, based on a 0.18-$mu{rm m}$ CMOS pro...
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A 2.4-GHz industrial scientific and medical band binary frequency-shift-keying transmitter embedded in the Hypothesis, Odyssey, and Yield (HOY) wireless test system is presented and implemented, based on a 0.18-$mu{rm m}$ CMOS process. With the digitally controlled oscillator (DCO) using a stacked-LC tank, this transmitter occupies an area of only 0.1 ${rm mm}^{2}$ and has a measured phase noise of ${-}{rm 111.8}~{rm dBc}/{rm Hz}$ at a 500-kHz offset. The effects of stacking a spiral inductor over the other circuits are considered and examined using two DCO test chips. Both the antenna and the power amplifier are eliminated as a result of the short distance of transmission. By adopting an open-loop modulation architecture, a data rate of 10 Mb/s can be achieved. For a supply voltage of 1.5 V, the power consumption is only 9.2 mW and the emission output power measured at a distance of 1 cm is greater than ${-}{rm 60}~{rm dBm}$.
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A measurement technique is proposed to conduct S-parameter measurements on symmetrical reciprocal three-port devices using a two-port vector network analyzer. The technique takes the effects of reflection from an unmeasured port t...
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A measurement technique is proposed to conduct S-parameter measurements on symmetrical reciprocal three-port devices using a two-port vector network analyzer. The technique takes the effects of reflection from an unmeasured port terminated with a non-ideal 50-$Omega$ load into consideration. These reflected signals cause errors in S-parameter measurements, especially at higher frequencies where the reflection is too large to be ignored. The errors have been overlooked in the traditional three-port measurement using two-port network analyzers. In this paper, analytic equations are presented for some common symmetrical reciprocal three-port devices to improve the accuracy of their S-parameter measurements. The improvement is justified by comparing the data before/after applying the proposed technique with the measured data from four-port vector network analyzers. In addition, error analysis is conducted to ensure that the errors introduced by vector network analyzers would not be deteriorated by the proposed equations.
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Demagnetization faults in permanent magnet synchronous motors may generate specific fault harmonic frequencies in the stator currents and the zero-sequence voltage component (ZSVC) spectra. Hence, by analyzing the stator currents ...
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Demagnetization faults in permanent magnet synchronous motors may generate specific fault harmonic frequencies in the stator currents and the zero-sequence voltage component (ZSVC) spectra. Hence, by analyzing the stator currents or/and the ZSVC spectra it is possible to develop fault diagnosis schemes to detect such faults. In order to have a broad view of such effects, a representative set of stator windings configurations must be considered. By analyzing different stator windings configurations this paper shows that the amplitude of the harmonic frequencies of both the stator currents and the ZSVC spectrato be analyzed are significantly influenced by the stator windings configuration. It is also proved that depending on the winding configuration, new harmonic components may emerge in both spectra. The results presented in this paper may help to develop fault diagnosis schemes based on the acquisition and further analysis of the stator currents and the ZSVC harmonic components.
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We propose optimal resource allocation techniques for two kinds of optical slot switching metro rings: 1) fixed mixed line rate (fMLR), where the rate of each transponder (TRX) is fixed and set at network planning time; and 2) ela...
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We propose optimal resource allocation techniques for two kinds of optical slot switching metro rings: 1) fixed mixed line rate (fMLR), where the rate of each transponder (TRX) is fixed and set at network planning time; and 2) elastic TRX, where the rate may adjust dynamically on a per-slot basis during network operation. We then numerically compare the cost (CAPEX or energy) of fMLR and elastic networks, and investigate the suitability of each of the two considered network technologies for several ring topologies, TRX cost models, and traffic distributions and loads.
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A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate ox...
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A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.
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In this study, a five-level inverter-based grid-connected power conversion interface is proposed. The output current of grid-connected power conversion interface is controlled to be sinusoidal and in phase with the utility voltage...
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In this study, a five-level inverter-based grid-connected power conversion interface is proposed. The output current of grid-connected power conversion interface is controlled to be sinusoidal and in phase with the utility voltage so as to perform the unity power factor. The grid-connected power conversion interface is configured by a DC??DC boost converter and a proposed five-level inverter. The DC??DC boost converter is employed to boost a lower DC voltage source. The presented five-level inverter is composed of a series/parallel capacitor set and a full-bridge converter. The presented five-level inverter contains only five power electronic switches, thus simplifying the circuit configuration. In addition, only one power electronic switch is switched in high frequency and only three semiconductor devices are conducting in series at the same time in the presented five-level inverter. Thus, the power loss will be reduced and the power efficiency will be improved. Moreover, the control for balancing the voltages of DC capacitors of the presented five-level inverter is simplified because the DC capacitors are discharged in series and in parallel alternately. A prototype is developed and tested to verify the performance of the proposed grid-connected power conversion interface. The experimental results show that the proposed grid-connected power conversion interface achieves the expected performance.
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There is an error in the order of the references [18] and [19] in the above-named article [ibid., vol. 61, no. 4, pp. 1533??1542, Apr. 2013]. The order of these references should be exchanged. The corrected order (and numbering) o...
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There is an error in the order of the references [18] and [19] in the above-named article [ibid., vol. 61, no. 4, pp. 1533??1542, Apr. 2013]. The order of these references should be exchanged. The corrected order (and numbering) of these two references are shown as follows: [18] J. Kim and J. F. Buckwalter, "A 92 GHz bandwidth distributed amplifier in a 45 nm SOI CMOS technology," IEEE Microw. Wireless Compon. Lett., vol. 21, no. 6, pp. 329??331, Jun. 2011. [19] A. Jahanian and P. Heydari, "A CMOS distributed amplifier with distributed active input balun using GBW and linearity enhancing techniques," IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, pp. 1331??1341, May 2012.
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